International Business Machines Corporation

Atmel Corporation

Globalfoundries Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Frank Ray Keyser, Iii

Scott Whitney Gould

Joseph Andrew Iadanza

Terrance John Zittritsch

Brian A Worth

Kim P Clinton

Steven Paul Hartman

Allan Robert Bertolet

Eric Ernest Millham

Victor Paul Seidel

Timothy Shawn Reny

Anthony Richard Bonaccio

Frederick Furtek

Ralph David Kilmoyer

Michael Joseph Laramie

Christine Marie Fuller

Wendell Ray Larsen

Gulson Yasar

Michael Anthony Sorna

Leonard R Chieco

Evangelos Stavros Eleftheriou

Roy Daron Cideciyan

Richard Leo Galbraith

Martin L Schmatz

Jonathan Darrel Coker

Robert E Busch

David John Craft

Benjamin T Voegeli

David James Stanek

Valerie Hornbeck Chickanosky

Allen Prescott Haar

Troy A Seman

Barton E Green

Sally S Botala

Ronald Raymond Palmer

Wayne Kevin Beebe

Benjamin T Voegli

A system and method for receiving includes an input multiplexer configured to select between one or more input data streams and a pseudo random bit sequence (PRBS) to provide a serial stream. A plurality of storage devices is configured to sample the serial stream. An output demultiplexer is configured to demultiplex the sampled serial stream into a plurality of output streams. A PRBS checker is configured to compare a PRBS pattern on the plurality of output streams with a predicted PRBS pattern. A phase rotator is configured to adjust a data control clock based upon the comparison of the PRBS checker to reduce latency in the receiver.

Receiver deserializer latency trim

A system and method for transmitting includes a plurality of multiplexers each configured to combine a pseudo random bit sequence (PRBS) with at least one input stream according to the data control clock. At least one storage device is coupled to an output of each of the plurality of multiplexers and is configured to latch data according to the data control clock. An output multiplexer is coupled to each of the at least one storage device and is configured to select between storage paths according to the data serializer clock. A PRBS checker is configured to compare a PRBS pattern on an output of the output multiplexer with a predicted PRBS pattern. A phase rotator is configured to adjust the data serializer clock based upon the comparison of the PRBS checker to reduce latency of the transmitter.

Transmitter serializer latency trim

A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.

Off-line gain calibration in a time-interleaved analog-to-digital converter

A successive approximation analog-to-digital converter (ADC) includes an adjustable voltage source that applies an adjustable voltage to an input of a comparator of the ADC to cancel an offset of the ADC. The ADC also includes a control that suspends adjustments of the adjustable voltage when the adjustable voltage converges on the offset. The adjustable voltage source is a digital-to-analog converter.

Comparator offset cancellation in a successive approximation analog-to-digital converter

An integrated circuit and a method of reconfiguring an integrated circuit in which multiple configuration sets, each including a plurality of register settings, are stored on the chip. Selection of at least a portion of a configuration set allows for quicker and easier retrieval and loading of register settings, and reduces the complexity and size of the higher level system control program. In an alternative embodiment, at least a portion of a configuration set that is stored on the chip can be directly loaded to at least one device to be controlled to eliminate the need for the set of registers.

Integrated circuit having register configuration sets

A read channel for a hard disk controller comprising: means for generating a sequence of start of write signals to individually control the start of writing of each of one or more servo sync words to a disk; and means for individually writing the one or more servo sync words to the disk.

Read channel with automatic servo track writer

Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.

Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Field programmable memory array

Programmable address decoder for field programmable memory array

Method of operating a field programmable memory array with a field

Programmable bit line drive modes for memory arrays

Memory cells for field programmable memory array

Selective connectivity between memory sub-arrays and a hierarchical bit

A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Testable programmable gate array and associated LSSD/deterministic test

Growing community of inventors

Colchester, VT, United States of America

Frank Ray Keyser, Iii