Texas Instruments Corporation

Frank R Fattori

Marco Corsi

Erich Bayer

Kevin Scoones

Derek Colman

Joseph D Farley

Walter Bucksch

Richard M Kerslake

A driver amplifier for a bus feeds single polarity signals of controlled slew rate to the bus. The slew rate control is effected by a feedback capacitor connected from the output to the input of the amplifier. A clamp is provided for selectively connecting the input of the amplifier through a low impedance path to a point of reference voltage so that when the amplifier is quiescent signals on the bus cannot be fed through the capacitor to turn on the amplifier. A current source and a switchable current sink are connected to the input of the amplifier to change the capacitor to produce the slew rate controlled transitions. Another driver amplifier of the same design but using components of the opposite conductivity type can be used to apply signals of the opposite polarity to the same bus.

Controlled slew rate bus driver circuit having a high impedance state

A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

High power MOS transistor

This invention relates to differential bus drivers for use in, for example, communication systems. The driver achieves highly symmetrical wave forms at the output stage for both high and low side drivers. In addition, the layout of components of the high and low side drivers is substantially identical which allows production of the driver as an integrated circuit with a simple layout.

Differential bus drivers

An integrated circuit having a first group of semiconductor components which use potentials which are positive with respect to the substrate and a second group of components which use potentials which are negative with respect to the substrate. A negative voltage regulator circuit suitable for use in telephone circuits is described in which the regulated output is produced at the substrate so that noise can be prevented from being capacitatively coupled from the substrate to the input stages of amplifiers in the same integrated circuit. The exemplary circuit is produced by the so-called BIDFET process and use both bipolar and field effect transistors. One semiconductor component described includes an enhancement mode MOSFET with a channel in the surface of an epitaxial layer and a drain region forming the base of a bipolar transistor using the epitaxial layer as a collector region, there being a highly doped buried layer of the same conductivity type as the epitaxial layer at the interface between it and the substrate which is of the opposite conductivity type.

Integrated circuit having bipolar transistors and field effect

A line interface circuit sends two-level signals to a line and receives two-level signals from a line. The two levels of the signals are on opposite sides of a threshold range of levels. For testing the circuit the transmitter is connected to the receiver by a switchable path, and a test signal is produced by the transmitter for reception by the receiver for monitoring the functioning of the circuit. The test signal is of a small amplitude so as not to enter the threshold range of levels). The connections of the transmitter and receiver to the line are maintained during testing. During testing the output of the transmitter is limited in amplitude by a voltage clamp so that it can produce only the test signal.

Growing community of inventors

Clapham, United Kingdom

Frank R Fattori