Sgs-thomson Microelectronics Limited

Stmicroelectronics Gmbh

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Mostek Corporation

Hewlett-packard Development, L.p.

Sgs-thomson

Frank R Bryant

Tsiu Chiu Chan

Robert L Hodges

Fusen E Chen

Loi Ngoc Nguyen

Girish A Dixit

Simon Dodd

Fu-Tai Liou

Che-Chia Wei

Danielle A Thomas

Artur P Balasinski

John L Walters

Yu-Pin Han

Paul I Mikulan

Abha Rani Singh

Joseph M Torgerson

Terry E McMahon

Angela White Bakkom

Charles R Spinner, Iii

Dennis W Tom

Richard Todd Miller

S Jonathan Wang

Gregory T Hindman

Mark Richard Tesauro

Murray J Robinson

Lun-Tseng Lu

Lisa K Jorgenson

Alexander Kalnitsky

James A Cunningham

Kuei-Wu Huang

Marco Sabatini

Frank J Sigmund

John E Turner

Kenneth Wayne Smiley

John L Waters

Paul W Ackmann

Terry E Mcmahon

A microfabricated structure that includes a first layer of material on a substrate, and a second layer of material over the first layer that forms an encapsulated cavity, and a structural support layer added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Micro-fluidic structure

An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated circuit is capable of performing one or more functions associated with the display of the content on the display panel. The apparatus further includes a controller capable of adjusting one or more characteristics of the display panel based on the amount of ambient light measured by the light sensor. The integrated circuit and the photo-sensitive device may be formed on one side of a semiconductor wafer, and the photo-sensitive device may be exposed to the ambient light through an opening in an opposing side of the semiconductor wafer.

Apparatus and method for adjusting a display using an integrated ambient light sensor

An apparatus is provided that includes a light source, an array of light-reflecting devices, and a processor for positioning the light-reflecting devices so as to display an image on the display screen. Each of the light-reflecting devices selectively reflects the light from the light source onto a corresponding pixel of a display screen. The processor positions a first of the light-reflecting devices such that light from the light source is reflected by the first light-reflecting device onto a first pixel of the display screen, which is different than the pixel of the display screen that corresponds to the first light-reflecting device. A similar apparatus is also provided in which the processor instead positions the first light-reflecting device such that light from the light source is reflected by the first light-reflecting device onto a first area of the display screen, which is located between the pixels of the display screen that correspond to the first light-reflecting device and an adjacent second light-reflecting device.

Method and system to automatically correct projected image defects

A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Transistor structure and method for making same

A microfabricated structure and method of making that includes forming a first layer of material on a substrate, forming patterned sacrificial material having a predetermined shape on the first layer of material, and forming a second layer of material over the first layer and the patterned sacrificial material, which is then removed to form an encapsulated cavity. Ideally, the first and second layers are formed of the same type material. A structural support layer can be added to the second layer. Openings can be formed in the cavity, and the cavities can be layered side by side, vertically stacked with interconnections via the openings, and a combination of both can be used to construct stacked arrays with interconnections throughout.

Method of making a micro-fluidic structure

A method of forming a semiconductor device, the method including forming a substrate including a first surface having a non-doped region, forming an insulative material over the first surface of the substrate, forming a first conductive material over the first insulative material, forming an opening in the first conductive material that forms a path to the substrate that is substantially free of the first conductive material and the first insulative material, forming a second insulative material over the first conductive material, and forming a second conductive material over the second insulative material, wherein the second conductive material is formed in the opening and contacts the non-doped region of the substrate.

Integrated circuit and method for manufacturing

Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.

Devices and methods for integrated circuit manufacturing

A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.

Structure for transistor devices in an SRAM cell

A fluid ejection device including: a substrate having a first surface having an non-doped region; a first insulative material disposed on a portion of the first surface, the first insulative material having a plurality of openings forming a path to the first surface; a first conductive material disposed on the first insulative material, the first conductive material being disposed so that the plurality of openings are substantially free of the first conductive material; a second insulative material disposed on the first conductive material and portions of the first insulative material, the second insulative material being disposed so that the plurality of openings are substantial free of the second insulative material and a second conductive material being disposed on second insulative material and within plurality of openings so that some of the second conductive material disposed upon the second insulative material is in electrical contact with the non-doped region on the substrate.

The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

Thin-film transistor used as heating element for microreaction chamber

Fluid ejection device including integrated circuit with shielding element

An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.

Printhead integrated circuit

Printhead with looped gate transistor structures

Growing community of inventors

Denton, TX, United States of America

Frank R Bryant