Advanced Micro Devices Corporation

Dell USA L P

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Frank P Helms

Maurice B Steinman

Larry David Hewitt

Scott E Swanstrom

Dale E Gulick

Alexander J Branover

William Alexander Hughes

Derrick R Meyer

Scott A White

Paul C Miranda

Paul Mackey

Alex Branover

Prashant U Kenkare

Alan E Brown

John P Petry

Jonathan Mercer Owen

Brian M Millar

Bill K C Kwan

W Kurt Lewchuk

Jeffrey A Brinkley

Kurt Lewchuk

Ross Voigt LaFetra

According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal.

Dual supply memory

Provided are an operating method of a semiconductor integrated circuit and a semiconductor integrated circuit which includes a core circuit. The operating method includes: monitoring respective residencies of operating states of the core circuit; and controlling the operating states of the core circuit according to the monitored residencies of the operating states.

Semiconductor integrated circuit and operating method of semiconductor integrated circuit

A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

Hardware monitoring and decision making for transitioning in and out of low-power state

A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.

Protocol for power state determination and demotion

A processor can operate in three different modes. In an active mode, a first voltage is provided to the processor, where the first voltage is sufficient to allow the processor to execute instructions. In a low-power mode, a retention voltage is provided to the processor. The processor consumes less power in the retention mode than in the active mode. In addition, the processor can operate in a third mode, where a voltage is provided to the processor sufficient to allow the processor to process cache messages, such as coherency messages, but not execute other normal operations or perform normal operations at a very low speed relative to their performance in the active mode.

Data processing device with low-power cache access mode

A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

Dynamic processor power management device and method thereof

A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

Selective deactivation of processor cores in multiple processor core systems

A serial communication system includes an integrated circuit having a master serial interface; and a processor having a slave serial interface coupled to the master serial interface through a clock signal line and a data signal line. The slave serial interface is responsive to a read temperature command issued by the master serial interface to return a first temperature value associated with the processor.

Serial interface having a read temperature command

A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Message based power management in a multi-processor system

An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

Use of a signal line to adjust width and/or frequency of a communication link during system operation

A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

Message based power management

Power management logic maintains memory in a computer system in the self refresh state during a power savings state in which power is removed from the memory controller. A memory control circuit, separate from the power management logic, controls the memory during other operational modes. The power management logic maintains the system memory in the self refresh state by driving memory control signal(s) at appropriate values during the power savings state.

Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system

The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases above a predetermined threshold, the maximum performance state available is reduced. Multiple temperature thresholds may be utilized providing for a gradually reduced maximum performance state as temperature increases. When the temperature returns to a lower level, the maximum performance state available is increased. Changing the maximum available performance state according to temperature provides for more gradual reduction in performance as temperature increases, which results in higher average system performance as temperature increases. Thus, a more gradual reduction in performance is provided while still maintaining a high speed rating of the processor in more ideal conditions. In normal operating conditions, high processor performance is provided, while slightly reduced performance is provided in abnormal operating conditions.

Variable maximum die temperature based on performance state

An integrated circuit provides for changes to its core clock frequency and its core voltage using software programmable registers on the processor to store voltage ID (VID) values to specify core voltage, which are supplied to a voltage regulator and clock frequency control values, which are supplied to clock generation logic on the integrated circuit to specify core clocks. The integrated circuit generates an internal state in which its core clocks are stopped or slowed and during which core voltage and core frequency are adjusted. The processor also includes a timing mechanism that allows the new voltage and clock frequency to stabilize before resuming core operations. The timing mechanism may include a programmable count to specify the time to allow the new voltage and clock frequency to stabilize.

Programmable stabilization interval for internal stop grant state during which core logic is supplied with clocks and power to minimize stabilization delay

Disclosed herein are a method and apparatus to provide a deterministic power-on voltage in a system having a processor-controlled voltage level. In one embodiment, the system includes a DC/DC converter, a processor, and a selection circuit. The DC/DC converter receives a voltage setting signal or signals from the selection circuit and provides an adjustable power output signal having a voltage indicated by the voltage setting signal. The processor is powered by the adjustable power output signal. When powered, the processor provides a programmable voltage setting signal or signals. The selection circuit receives the programmable voltage setting signal or signals, a hardwired voltage setting signal, and a selection signal or signals, and when the selection signal is in a predetermined condition, the selection circuit provides the programmable voltage setting signal or signals from the processor to the DC/DC converter. Preferably, when the selection signal is in a second predetermined condition complementary to the first predetermined condition, the circuit provides the hardwired voltage setting signal to the DC/DC converter. The first and second predetermined conditions of the selection signal are preferably de-assertion and assertion, respectively. The selection signal may be determined by a logic gate that combines a mode control signal and a power good signal, and causes the selection signal to select the voltage setting signal from the processor only when the power good signal is asserted and the mode control signal is de-asserted. This advantageously allows for the processor to dictate its operating voltage level, an ability that is extremely useful for power and thermal management in notebook PCs.

Growing community of inventors

Round Rock, TX, United States of America

Frank P Helms