Raytheon Company

Frank N Cheung

Robert J Coda

Hector Q Gonzalez

Pen C Chien

Kuan Y Huang

Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Inter-processor memory

An imaging system disables pixel integration for images within frames that are identified as moving while enables pixel integration for images that are not moving. The system may implement a frame-averaging type of integration or recursive types of frame integration, or may refrain from performing frame integration. On a pixel-by-pixel basis, the system may compare a pixel from frame memory with a corresponding pixel of an input frame and may disable pixel integration for the pixel when a difference between the compared pixels exceeds a threshold. One of the integration processes may be performed on the pixels when the difference does not exceed the threshold. When frame integration is disabled or de-selected (e.g., for pixels having motion), the frame memory may be bypassed and a self-integration may be performed with corresponding pixels from a current frame effectively resulting in no integration. Some embodiments may use multiple thresholds, and may use different integration algorithms depending on conditions within a scene.

Method and imaging system with intelligent frame integration

A system () and method for outputting data from a detector (). The novel system () includes a first controller () that samples the detector () at a first rate, a memory () for storing the sampled data, and a second controller () that outputs data from the memory () at a second rate. In a illustrative embodiment, the first rate is symmetrical from field to field, while the second rate is asymmetrical from field to field.

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Agoura Hills, CA, United States of America

Frank N Cheung