International Business Machines Corporation

Frank Musante

Alexander Joel Suess

Louise Helen Trevillyan

Nathaniel Douglas Hieter

Michael Kazda

Gi-Joon Nam

Paul Gerard Villarrubia

Gustavo Enrique Tellez

Lakshmi Narasimha Reddy

Michael H Wood

Shyam Ramji

Anthony DeGroff Drumm

Jagannathan Narasimhan

Sean Michael Carey

Jinwook Jung

Ofer Geva

Pooja M Kotecha

Cindy ShuiKing Washburn

Veena S Pureswaran

William E Dougherty

Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.

Netlist design for post silicon local clock controller timing improvement

A system to develop an integrated circuit includes a latch identifier module to identify a first child latch placed at a first location in a first child macro of a parent macro and a second child latch placed at a second location in a second child macro of the parent macro. The second child latch is located away from the first child latch. The system further includes a latch location optimization module and a latch placement module. The latch location optimization module determines a target timing parameter threshold and determines a first actual timing parameter. The latch placement module changes the first location of the first child latch and/or the second location of the second child latch to generate an optimized parent macro based on the changed locations. The latch location optimization module re-executes the latch optimization process to determine a second actual timing parameter based on the changed locations.

Out-of-context feedback hierarchical large block synthesis (HLBS) optimization

A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Critical path straightening system based on free-space aware and timing driven incremental placement

Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining 'non-critical' circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical circuit components in a new partial placement image of said map; and reinserting the 'non -critical' circuit components back into said placement image. The optimization is performed by circuit transformation operating in congested regions of the placement image enabling cell insertion and modifications that increase cell size.

Method of improving timing critical cells for physical design in the presence of local placement congestion

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

Task-based multi-process design synthesis with notification of transform signatures

A method of performing a static timing analysis based on slack values to verify and optimize a logic design includes: selecting one or more circuits within the logic design having at least two inputs taking on a known value; identifying a critical input that controls an output arrival time of the selected circuit from among the inputs that take on the known value; determining one or more non-critical input of the circuit a required arrival time based on the difference between the arrival times of the critical and non-critical inputs; and computing the slack at a critical input based on the difference between the AT of the critical and non-critical inputs. The design optimization based on the slack defined by arrival time differences preferably uses a reverse merge margin design metric. The metric determines the exact required amount of improvement in the input arrival time of non-critical signals of a clock shaping circuit.

Method for enabling multiple incompatible or costly timing environment for efficient timing closure

A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design.

Method of minimizing early-mode violations causing minimum impact to a chip design

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Poughkeepsie, NY, United States of America

Frank Musante