Pact Xpp Technologies Ag

Other

Hyperion Core, Inc.

Scientia Sol Mentis Ag

Pact Xpp Schweiz Ag

Krass, Maren

Richter, Thomas

Frank May

Martin Andreas Vorbach

Armin Nückel

Volker Baumgarte

Markus Weinhardt

Gerd Ehlers

Prashant Rao

Jens Oertel

Dirk Reichardt

Frank Lier

Jürgen Becker

Joao Manuel Paiva Cardoso

A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Issuing instructions to multiple execution units

An integrated data processing core and a data processor are provided on a single integrated circuit and command sequences are forwarded from the data processing core to be executed on the array data processor wherein the command sequences comprise a group of instructions defining an algorithm.

Integrated data processing core and array data processor and method for processing algorithms

A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.

Method of transferring data between external devices and an array processor

A method for operating a system on a chip comprising a conventional processor unit (CISC, RISC, VLIW, DSP) and an array processor having a multidimensional arrangement of arithmetic units. Operation information for the array processor are stored in a memory shared between the conventional processor and the array processor. At runtime the conventional processor points the array processor to the memory area comprising the operation information. A management unit inside the array processor is autonomously loading the operation information into the array processor.

Method for processing data

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Array processor having a segmented bus system

An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Methods and systems for transferring data between a processing device and external devices

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Data processor chip with flexible bus system

A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.

Multi-processor bus and cache interconnection system

A data processing system having a data processing core and integrated pipelined array data processor and a buffer for storing list of algorithms for processing by the pipelined array data processor.

Data processing system having integrated pipelined array data processor

The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.

Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file

A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel.

Method of processing data with an array of data processors according to application ID

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Logical cell array and bus system

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Growing community of inventors

Munich, Germany

Frank May