Integrated Device Technology, Inc.

Depuy Products, Inc.

Frank Matthews

Jessica Ye

Chenhao Geng

Mark R DiSilvestro

John E Slamin

Terry L Dietz

Angus David Starr MacAdam

Duy Pham

Ivan Hsiao

Ordin Kuo

Dinh Bui

Paul Tomaszewski

Alexander P Goldhammer

Wallace Ly

Eric Leung

Bob Hastings

Tony Petrella

Dave MacAdam

Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock signal to the processor. At least one of the processor voltage regulator or the system clock generator is further configured determine a desired frequency of the system clock signal responsive to the present processor load state, and determine a voltage level for the core voltage signal suitably paired with the desired frequency for proper operation of the processor at the desired frequency. Other systems, apparatuses, and methods are provided.

Systems, apparatuses and methods for dynamic voltage and frequency control of components used in a computer system

A telemetric tibial tray includes a lower plate that defines a plurality of cylindrical transducer cavities having circular load diaphragms. An upper plate is attached to the lower plate through support posts projecting from the load diaphragms. The support posts have a circular cross-section and a diameter of about 5.0 mm. The lower plate further defines wiring channels communicating between the transducer cavities and a central cavity housing the circuit board for the telemetric tray. The wiring channels are arranged at a 45 degree angle relative to the sagittal plane of the knee joint in order to reduce the effects of the wiring channel intersection on the strain sensitivity of the tray. Each transducer cavity includes a radial strain gage array with four pairs of radially aligned strain gages, each pair aligned at a 45 degree angle relative to the sagittal plane of the knee joint. Each pair of strain gages includes an inner gage positioned at the point of maximum positive micro-strain across the diaphragm when loaded, and an outer gage positioned at the point of maximum negative micro-strain, to thereby increase the differential strain measured by the gages and increase the strain sensitivity of the tibial tray.

Telemetric tibial tray

Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.

Time-slot interchange switches having group-based output drive enable control and group-based rate matching and output enable indication capability

Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.

Data memory address generation for time-slot interchange switches

Asynchronous memory devices utilize loopback circuitry to provide efficient and high speed 'flow-through' of write data when conventional flow-through operations are not available. An exemplary memory device includes a memory array having first and second ports that can each support asynchronous read and write access and a first input/output control circuit. The first input/output control circuit is electrically coupled to the first port and includes a first sense amplifier, which is configured to receive read data from the first port, and a first bypass latch having an output coupled to the first sense amplifier. A second input/output control circuit is also provided. The second input/output control circuit is electrically coupled to the second port and includes a second sense amplifier, which is configured to receive read data from the second port, and a second bypass latch.

Integrated circuit memory devices having asynchronous flow-through capability

Embodiments of the present invention may provide methods of controlling a memory device and memory devices including a memory array having an internal address input which specifies a location in the memory array accessed during read operations and write operations. An external address input receives an address value from a device external to the memory device. The received address value may be utilized to randomly access the memory array. An address register/restart address counter is operatively associated with the memory array and the external address input and configured to store a start address for at least a write operation to the memory array, to selectively generate a series of internal addresses to access the memory array based on the stored start address and to selectively return to the stored start address as a start address of a subsequent operation to access the memory array.

Memory devices having a restore start address counter

Growing community of inventors

Alpharetta, GA, United States of America

Frank Matthews