National Semiconductor Corporation

Frank Marazita

Rick C Jerome

Brian McFarlane

John E Readdie

Ali A Iranmanesh

George E Ganschow

Ronald P Kovacs

Lawrence K Lam

James L Bouknight

A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

Transistor device with increased breakdown voltage

A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium. Mass transport of aluminum atoms through the polysilicon allows aluminum to collect at an interface between the polysilicon and an underlying single crystal silicon layer. Aluminum atoms are supplied from a contact metal. A barrier metal between the contact metal and an underlying polysilicon contact to the emitter is not present. Inhibiting or replacing a TiSi.sub.2 layer over the fuse emitter contact provides better reproducible fusing action. PtSi replaces TiSi.sub.2 if formed over the fuse emitter contact. Separate fuse base implants for the vertical fuse change BJT parameters for improved fusing characteristics. In still another preferred embodiment, codiffusing N type and P type dopants from the polysilicon emitter contact drops a separate fuse mask. The P type codiffused dopants diffuse ahead of the N type emitter dopants into the single crystal to change the base parameters to provide a decreased gain.

Vertical fuse device

A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon layer into the N- base region. The base region thus remains N- and the resulting transistor has improved breakdown voltage characteristics while retaining the speed advantages of polysilicon contact layers. The lateral pnp transistor is manufactured by a method which requires minimal deviation from other methods used to manufacture lateral pnp transistors.

High breakdown lateral PNP transistor

Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Low resistance silicided substrate contact

A method for fabricating a diode, for example, for use in a Schottky clamped transistor, which as a process step disposes a layer of oxide between the substrate and the overlying layer of polysilicon which must ultimately be etched away. The oxide layer permits use of an end point dry etch process which in turn allows greater miniaturization of the circuit over wet etch processes. Use of the end point process made feasible by the oxide layer also prevents overetch of the silicon material. As a result, a more ideal metal silicide anode-to-substrate Schottky barrier is formed with corresponding improvements in the diode ideality factor. In addition the oxide layer eliminates Schottky mask alignment problems and further improves diode performance characteristics by elimination of parasitic diodes. The process can be implemented with minimal deviation from other core processes used to fabricate similar circuits.

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San Jose, CA, United States of America

Frank Marazita