Xerox Corporation

Other

Frank M Nelson

Kenneth Gillett

John W Daughton

George E Mager

Stephen P Wilczek

Andrew T Ling

Charles P Holt

Richard M Malinich

Warren L Hall

Edward L Steiner

James M Donohue

Vinod K Kadakia

Thanh D Truong

Kenton W Fiske

Donald S Post

Philip Richardson

Thomas Criswell

Steven L Reid

Vernon E Rochat

James J Donohue

A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

Interleaved Huffman encoding and decoding method

A data communication system having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.

Serial data communication system having simplex/duplex interface

A data communications system having a programmable master controller including memory means and command byte generating means and a plurality of additional controllers providing input data bytes to the master controller and having means for receiving command bytes from the master controller. The additional controllers are each connected to the master controller such that corresponding data bits are ORed together and means are provided for the simultaneous transmission of data bytes from the additional controllers to the master controller such that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

Programmable master controller communicating with plural controllers

An electrophotographic reproduction machine for use as a copier/duplicator having a master microprogrammed controller and a plurality of area controllers cooperatively operative to carry out a plurality of machine operation tasks. At least one of the area controllers contains a separate microprogrammed controller for controlling selected tasks and devices in the reproduction machine in synchronism with the operation of other tasks as controlled by the master controller. An optical communication link couples the master and area controllers and serves to isolate the master controller from transients and a direct I/O connection.

Distributed microprocessor control system for a copier/duplicator

A data communications system for an electrophotographic type reproduction machine or copier. The system includes a programmable master controller with memory and a command byte generator. A plurality of secondary controllers provide input data bytes reflecting the machine status to the master controller and receive command bytes from the master controller for operating the machine components. The secondary controllers are each connected to the master controller such that corresponding data bits of the secondary controller are ORed together to provide simultaneous transmission of input data bytes from the secondary controllers to the master controller while assuring that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

Data communications system for a reproduction machine having a master

A data communication system for an electrophotographic type reproduction machine or copier having a master unit, an interface, and one or more remote units. The master unit includes a programmable controller having a data processor, memory storage for storing programs and command and data bytes, and address and data buses. The interface is connected to the master unit via the address and data buses, and includes a memory connected to the data bus for temporarily storing command and output data bytes from the master unit pending transmittal thereof to the remote units and for storing input data bytes from the remote units pending transfer thereof to the master unit. A first communication path, along which command and data bytes from the interface memory are transmitted to the remote units, couples the interface with the remote units. A second communication path, along which input data bytes from the remote units to the interface memory are transmitted, couples the remote units with the interface.

Serial data communication system for a reproduction machine

A reproduction machine having a plurality of operating stations and a plurality of devices for controlling operational tasks of said operating stations comprising a master controller having an arithmetic and logic unit for controlling the devices in accordance with sensed operational parameters and a stored operation program and interface means connected in a communication path between the master controller and the devices. The interface means comprises a fiber-optic communication path for isolating the master controller from electrical noise and transients of the devices.

Reproduction machine using fiber optics communication system

An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

Auxiliary ROM memory system

In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.

Direct memory access module for a controller

In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus. The timed protocol unit comprises an address control coupled through the system bus to the central processor for disenabling address signals upon receipt of the first acknowledgement signal on the system bus from the diriment element, and a data control coupled through the system bus to the central processor for bidirectionally disenabling data signals upon receipt of the second acknowledge signal on the system bus from the diriment element.

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Sherman Oaks, CA, United States of America

Frank M Nelson