International Business Machines Corporation

Frank M Masci

Jack A Dorler

Dennis C Banker

Paul David Hendricks

Walter S Klara

Allan Harvey Dansky

Steven John Zier

James R Struk

Adrian Zuckerman

Stephen J Tytran

Tore A Carlson

Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The 'inverse' mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode. Transistors embodying the invention may be used to provide relatively constant current sources to numerous utilization means, such as logic or analog circuits. Due to the low VCEi of the 'inverse' mode transistor, the resultant circuits can be operated at a lower operating voltage than prior art circuits. This results in a decrease of power dissipation.

Integrated circuit employing inverse transistors

NOR logic performed by a half current switch emitter follower ('HCSEF') circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ('CSEF') circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.

NOR.sub.i circuit/bias generator combination compatible with CSEF

A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits. In a preferred embodiment, the circuit further includes a device for preventing a voltage differential of more than a predetermined amount between the base and emitter of the first bipolar transistor, to thereby ensure proper push-pull operation of the bipolar transistors.

BIFET logic circuit

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Wappingers Falls, NY, United States of America

Frank M Masci