Dell Products Inc.

Dell USA L P

Frank L Wu

Allen Chester Wynn

Anil Venkatasubba Rao

Roger M Blood

Armando Jaime Martinez

Shaojie Li

Fang Lu

George Mathew

Madhusudhan Rangarajan

In an information handling system, when a memory location is accessed and there is a bit error detected in that memory location then the memory location is logged into an error-log. The memory locations of the logged bit errors stored in the error-log are evaluated to determine whether there is one or more bit errors in a particular memory range, e.g., a contiguous range of memory locations. If there is one or more bit errors in a memory range, then that memory range may be hot ejected, e.g., disabled from use by the operating system. The bit error may be single bit error and/or multiple bit errors of a memory location.

Tolerating memory errors by hot ejecting portions of memory

A system and method for remotely updating a system BIOS. The method includes the steps of providing an updated BIOS to the remote computer system, storing the updated BIOS in a storage device of the remote computer system, setting a BIOS update indicator, rebooting the remote computer system and determining that the BIOS update indicator has been set, replacing the system BIOS with the updated BIOS, and rebooting the remote computer system again. The storage device may be hard drive, with the updated BIOS being stored in an EFI partition of the hard drive.

System and method for performing remote BIOS updates

A system with capabilities for recovering from memory errors includes memory and a processor in communication with the memory. The system also includes an operating system and a BIOS which reside in the memory and are executable by the processor. The BIOS includes recovery logic that detects a memory error in a section of the memory and, in response, instructs the operating system to discontinue use of the section of memory with the memory error. For instance, the system may include multiple memory objects that represent respective sections of the memory. The recovery logic may instruct the operating system to discontinue use of the section of memory with the memory error by sending an eject event to the operating system.

System and method for recovering from memory errors

A system and method for updating or synchronizing BIOS information for a multiple-node computer system is disclosed. Each node contains at least one processor, and a BIOS is associated with each processor. The BIOS in a node may be synchronized with the BIOS of another node such that BIOS coherence may be maintained between two or more nodes in the system. The computer system may be configured as an aggregated or partitioned system.

System and method for updating BIOS for a multiple-node computer system

A method of recovering from basic input/output system (BIOS) corruption operates in a multi-node computer system (MCS). The MCS includes first and second nodes, a first firmware unit in the first node, and a second firmware unit in the second node. According to the method, in response to initiation of a boot sequence for the MCS, the MCS automatically checks a BIOS image in the first firmware unit in the first node for corruption. In response to detecting corruption of the BIOS image in the first firmware unit, the MCS automatically recovers from the corruption by causing a good BIOS image to be copied from the second firmware unit in the second node to the first firmware unit in the first node. In one example embodiment, the MCS may contain multiple nodes, and the MCS may automatically recover from BIOS errors if any node contains a good BIOS image.

Automatic BIOS recovery in a multi-node computer system

The present disclosure describes a system and method for testing component IC chips. The system includes a management controller that has an embedded JTAG test routine operable to test one or more component IC chips associated with the management controller. The system further includes a memory associated with the management controller and the management controller is further operable to save a JTAG test routine result within the memory. More specifically, the management controller is operable to test one or more associated component IC chips using the embedded JTAG test routine during boot up of the system.

System and method for testing component IC chips

Methods and system for providing selectable initialization sequences are disclosed. The method of initializing a system includes providing at least one reference associated with a device coupled to the system. A user selects the reference associated with the device and an initialization sequence is determined based upon the selected reference.

System and methods for providing selectable initialization sequences

A computer systems implemented with I O devices having no Option ROM associated therewith needs to boot an OS from such an I O device without restricting the arrangement of the system BIOS boot sequence. A Virtual Option ROM is integrated into the system BIOS boot sequence code so that the BIOS can detect an I O device, and then get instructions from the Virtual Option ROM to initialize an I O Platform of an I O subsystem, wherein the I O device resides. Once the communication between the I O subsystem and the BIOS is subsequently achieved, the OS can be booted from the I O device. Further, by implementing the Virtual ROM, an I O device having no real Option ROM attached thereto can also be identified and used as a system boot device in a selective boot process. The initialization process of an IOP is skipped if a non-I O bootable device has been found before the detection of an I O device during the Power On Self Test.

Apparatus and method for booting a computer operation system from an intelligent input/output device having no option ROM with a virtual option ROM stored in computer

Growing community of inventors

Austin, TX, United States of America

Frank L Wu