Texas Instruments Corporation

Legerity, Inc.

Frank L Thiel

William E Moore

Baoson Nguyen

Michael R Kay

Philip S Shiota

Marco Corsi

Louis N Hutter

Fernando D Carvajal

Todd M Neale

Ranadeep Dutta

Bruce Webb

The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.

Methods of forming a P-well in an integrated circuit device

A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.

Bipolar junction transistor incorporating integral field plate

A semiconductor process is disclosed which forms openings in a dielectric layer through which the base region of both high-voltage and high-gain bipolar transistors are formed. In one embodiment of the invention, the openings for the high-gain transistors are first protected by a photoresist layer that is patterned to expose the openings for the high-voltage transistors. A first base implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the openings for the high-gain devices, and a second base implant is performed, this time into both base regions, and then diffused to a suitable depth. Emitter regions are then formed within the base regions of both transistor types by traditional implantation and contact techniques. Since the two base implants for each high-voltage transistor are self-aligned to a single opening through the dielectric layer, excellent control and repeatability is achieved for the high-voltage transistors. Moreover, since the second base implant is common to both types of transistors, many of the characteristics of the two types of transistors are well matched to each other.

Self-aligned dual-base semiconductor process and structure incorporating multiple bipolar device types

A semiconductor process is disclosed which forms openings in a dielectric layer through which the emitter region and collector region of lateral bipolar junction transistors are formed. In one embodiment of the invention, the emitter openings for the lateral bipolar junction transistors are first protected by a photoresist layer that is patterned to expose the collector openings for the transistors. A first implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the emitter openings, and a second implant is performed, this time into both the collector and the emitter regions, and then diffused to a suitable depth that is shallower than the first implant (used in the collector). Since the two implants are aligned to openings through the dielectric layer defined typically by a single mask, excellent base-width control and repeatability is achieved for the lateral transistors. Through careful selection of the collector and emitter diffusion profiles (i.e., depth and concentration), a more optimal PNP transistor may be constructed that has a collector deeper than its emitter. This scheme provides far greater collection efficiency than a traditional lateral PNP transistor made of the same diffusion for both the emitter and the collector. Greater collection efficiency provides improved Beta, better gain matching, and less parasitic loss of injected holes to a surrounding P-type junction isolation.

Lateral bipolar junction transistor with reduced parasitic current loss

A low-power op-amp circuit (70) having boosted bandwidth comprises a DC circuit block (72) which is coupled to first (V.sub.DC +, V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes and to an output node (V.sub.OUT) of an output stage (90). The DC circuit block (72) amplifies a differential signal received from the first (V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes, and provides an amplified signal to the output node (V.sub.OUT). An AC circuit block (74) is coupled to the output (NODE 3) of the DC circuit block (72). The AC circuit block (74) is operable to monitor a transient change between the first (V.sub.DC +, V.sub.AC +) and the second (V.sub.DC -, V.sub.AC -) input nodes. The AC circuit block (74) is further operable to transfer charge to the output node (V.sub.OUT) in response to the transient change, thereby providing boosted bandwidth beyond that of the DC circuit block (72) alone.

Low power op-amp circuit with boosted bandwidth

A semiconductor transistor device includes a first doped region 34 of a first conductivity type; a second doped region 30 of the first conductivity type formed at the surface of the first doped region 34, the second doped region 30 has a higher doping concentration than the first doped region 34; a source region 24 of a second conductivity type formed at the surface of the second doped region 30; a lightly doped drain region 28 of the second conductivity type surrounding the first doped region 34, the lightly doped drain region 28 has a lower doping concentration than the source region 24, the lightly doped drain region 28 is spaced apart from the second doped region 30; a buried layer 40 of the second conductivity type below the first doped region 34 and coupled to the lightly doped drain region 28; and a gate 32 overlying and spaced apart from the first doped region 34 and the second doped region 30.

High-voltage isolated high output impedance NMOS

An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comparator also includes an hysteresis stage 12 coupled to one of the current mirror transistors; the hysteresis stage comprises an hysteresis mirror transistor 34 and a switching transistor 36. The comparator additionally includes a gain stage 14 comprising a gain transistor 38 and a constant current source transistor 40. Finally, the comparator includes an output stage 15 comprising gain transistor 42 in an open-drain configuration. In the disclosed embodiment, the descending trip threshold is set entirely by the ratios of device geometries, and is therefore very accurate and is independent of temperature, lithography and processing variations. While the ascending trip threshold is related to the ratio of tail current of the differential pair to the transistor gain of the devices in that pair, which quantities are dependent on the device parameters, this relationship is only to the one-half power, and therefore is relatively small.

Low current comparator with hysteresis

A rapid start-up voltage reference (8) is provided. The rapid start-up voltage reference (8) includes a voltage reference circuit (10) operable responsive to a shut-down signal ENABLE. The shut-down signal has an enable state and a disable state. The voltage reference circuit (10) has a feedback loop (12) which has a first node (NODE 1). The voltage reference circuit (10) is operable to produce an output reference voltage (V.sub.REF) when the shut-down signal is in the enable state. A rapid start-up circuit (14) is coupled to the first node (NODE 1) and to a power supply node (V.sub.cc). The rapid start-up circuit (14) includes a capacitor (16) and is operable responsive to the shut-down signal to charge the capacitor (16) when the shut-down signal is in the disable state and to connect the capacitor (16) to the first node (NODE 1) when the shut-down signal is in the enable state.

Rapid start-up circuit for voltage reference and method of operation

The voltage regulator circuit contains a MOS transistor 12 connected between a voltage supply line 22 and an output line 30. The MOS transistor 12 provides a stable voltage on the output line 30 independent of voltage transients on the voltage supply line 22 and independent of current transients on the output line 30. An amplifier 14 coupled to the MOS transistor 12 controls the response of the MOS transistor 12. Feedback circuitry connected between the output line 30 and the amplifier 14 provides feedback to the amplifier 14. A voltage source 16 provides the reference for amplifier 14.

Ultra-low drop-out monolithic voltage regulator

An input protection circuit for a MOS device uses back-to-back zener diodes 30 and 40 with the anodes 130 and 150 connected and floating. This circuitry protects against positive and negative ESD events and does not interfere with the normal operation of the MOS device. The inventive circuit allows an improved gate operating range of the forward bias voltage of a first diode 30 plus the breakdown voltage of a second diode 40 below the supply voltage to the breakdown voltage of the first diode 30 plus the forward bias voltage of the second diode 40 above the supply voltage.

Structure for protecting integrated circuits from electro-static

An oscillator is provided for use in integrated circuits of the type that are employed in various, relatively low power, power management systems such as can be found in mobile communications systems and the like. The oscillator provides an output frequency that is highly stable over a range of conventional operational parameters. The oscillator provides a current generator that is comprised of a pair of NMOS transistors and a pair of PMOS transistors that are arranged such that the respective gates of each pair are connected to one another to establish current mirroring. The current generator is connected to a hysteresis circuit, which is operable to develop a potential difference in the circuit. The hysteresis circuit includes an NMOS transistor and a PMOS transistor that are respectively and correspondingly coupled to the current-mirroring NMOS and PMOS transistor pairs of the current generator. The hysteresis circuit also includes second, gate-connected NMOS and PMOS transistors and a switch array that is comprised of connected NMOS/PMOS transistor pairs. The NMOS/PMOS transistor pairs of the switch are operable in tandem such that no more than one of the NMOS/PMOS transistor pairs is closed at any time during operation of the circuit. A feedback control system is provided to regulate oscillator switch operation.

Oscillator compensated for improved frequency stability

A voltage reference circuit (2) is provided that operates with a minimal amount of headroom. A low threshold voltage transistor (M71) is incorporated into a bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) to eliminate base current errors that a current mirror (Q3 and Q4) of the bandgap may introduce. A low threshold voltage transistor (M72) is incorporated into the gain circuit (Q7) to eliminate base current error that a gain transistor (Q7) may introduce. A third low voltage transistor (M73) may be incorporated into a feedback circuit (QS) to eliminate any voltage variations possibly caused by the addition of the first two low threshold transistors (M71 and M72). Using P channel type MOS low voltage threshold transistors for base drive cancellation allows the circuit to operate effectively with a very low input voltage of around about 2.0 volts. These CMOS low threshold devices absorb process variations in the transistors that may occur between different lots of silicon and thereby provide a more manufacturable voltage reference circuit.

Low headroom manufacturable bandgap voltage reference

A switchable, uninterruptible, low-current reference generator with zero off-state current includes a cross-coupled, cascodeal .increment.V.sub.be current reference (70,72,74,76,78) for providing an output current, a current mirror (66,68) coupled in a cascode configuration with the current reference, and a start-up circuit (12) responsive to the absence of the output current for generating a start-up current (I.sub.58) to the current mirror. Start-up current is disabled when output current is restored, and the current mirror bootstraps the output current into regulation. Standby logic (10), comprising FET's configured as CMOS inverters, provides a TTL-compatible, active-low input, and switching FET's (60,80,90,92,94) responsive to the standby logic ensure that the reference generator draws no current in its off state. When the reference generator is turned on, a hysteresis circuit (98,52) coupled to the standby logic (10) increases the input voltage required for turn-off. The disclosed reference generator provides a bias current with a very low temperature coefficient and very little supply dependence. It has an active-low logic implementation with switching near the TTL range. It uses very little overhead current, and it cannot be forced permanently out of regulation by system transients. Because the start-up scheme uses actual detection of the absence of a bias current as its trigger, the reference generator will restart without the need for power supply ramping in the event of loss of bias during operation.

Switchable, uninterruptible reference generator with low bias current

A voltage reference circuit (2) is provided which includes a 2nd order curvature correction circuit (3) that eliminates undesirable 2nd order polynomial temperature dependency characteristics. A bandgap reference circuit (Q4, Q3, Q2, Q1, R2 and R1) forms a bandgap current (I.sub.X) that is dependent upon absolute temperature. A translinear cell (Q15, Q14, Q13, Q12, Q11 and Q10) transforms this current in a squaring transformation and divides the squared current by a temperature independent current (I.sub.X). A current mirror (Q17 and Q16) adjusts the value of the squared current so that it approximates the value of the 2nd order term of the bandgap reference circuit.

Growing community of inventors

Austin, TX, United States of America

Frank L Thiel