Texas Instruments Corporation

Frank L Laczko, Sr

Gerard V Benbassat

Jonathan L Rowlands

Stephen H Li

Karen L Walker

Stephen (Hsiao Yi) Li

Shiu Wai Kam

Edward E Ferguson

Kenneth R Cyr

Masashi Hashimoto

Gerard Chauvel

Serge Bernard Lasserre

Donald Edward Steiss

Brian Okchon Chae

Tiemen T Spits

Mario Giani

Y Paul Chiang

Dong-Seok Youm

Mark E Paley

Maria B H Gill

Fuk Ho Pius Ng

Paul M Look

Stephen (Hsiao Li

Yetung Paul Chiang

David (Shiu) W Kam

David (Shiu Kam

Maria Bh Gill

A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasksdetermine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint registeris sufficient to monitor addresses as they are provided by an address registerfor accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

Input/output buffer managed by sorted breakpoint hardware/software

A secure computing system stores a program, preferably the real time operating system, that is encrypted with a private key. A boot ROM on the same integrated circuit as the data processor and inaccessible from outside includes an initialization program and a public key corresponding to the private key. On initialization the boot ROM decrypts at least a verification portion of the program. This enables verification or non-verification of the security of the program. The boot ROM may store additional public keys for verification of application programs following verification of the real time operating system. Alternatively, these additional public keys may be stored in the nonvolatile memory. On verification of the security of the program, normal operation is enabled. On non-verification, system could be disabled, or that application program could be disabled. The system could notify the system vendor of the security violation using the modem of the secure computing system. This technique is applicable to downloaded programs could be applied to after sale acquired application programs. On downloading the after acquired program they decrypted using an additional public key.

Secure computing device having boot read only memory verification of program code

The method of secure computing concerns the security of a debugger/emulator tool commonly employed in program development. A private encryption key is used to encrypt at least verification token for the program. A public decryption key corresponding to the private encryption key is stored at the secure computing system. Upon each initialization of the debugger/emulator the secure computer system decrypts the verification token employing public decryption key. This indicates whether the program is secure or nonsecure. If the program is secure, then the debugger/emulator is operated in a process mode permitting access to the program while prohibiting access to at least one security feature. If the program is nonsecure, then the debugger/emulator is operated in a raw mode permitting access to all features of the secure computing system.

Program debugging system for secure computing device having secure and non-secure modes

A secure computing system prevents unauthorized use of compressed video data stored in a first-in-first-out memory buffer in a set top box. A single integrated circuit includes a data processor and a chip identity read only register storing a unique chip identity number fixed during manufacture. The data processor encrypts the compressed video data stream using the chip identity number as an encryption key. This encrypted data is stored in and recalled from a FIFO buffer. The data processor then decrypts the recalled data employing at least a part of the chip identity number as the decryption key. Using technique the compressed video data stream temporarily stored in compressed form in the FIFO buffer can only be employed by the particular data processor having the unique chip identity number.

Compresses video decompression system with encryption of compressed data stored in video buffer

A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.

Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory

An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.

Audio and video decoder circuit and system

A data processing device uses a portion of a random access memory as an output buffer for holding a frame of PCM sample data which is being output after being processed by a processing unit within the processing device. Fine grained synchronization between a reference clock and a stream of PCM data frames is provided by transferring only a portion of selected frame of PCM sample data PCM(n&plus;1), in response to a time difference,A breakpoint address is determined to delineate the portion of the selected frame that is to be transferred. A sorted list of the addresses of the discontinuities is maintained in breakpoint queue. Since the buffer is managed in a FIFO manner, a single breakpoint register is sufficient to monitor addresses as they are provided by an address register for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

Fine-grained synchronization of a decompressed audio stream by skipping or repeating a variable number of samples from a frame

An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.

Real time window address calculation for on-screen display

Secure computing device including operating system stored in non-relocatable page of memory

A video decoder having an input buffer for receiving an encoded and compressed data stream, parsing circuitry for removing header information from said data stream, circuitry for decoding said data stream, circuitry for decompressing said data stream, circuitry for selecting predetermined portions of preselected frames, memory for storing said decompressed data stream and selected portions of said preselected frames, and circuitry for reconstructing selected portions of said preselected frames is provided.

Reduced memory MPEG video decoder circuits and methods

An improved integrated circuit including decryption functions employs a method for determining if its environment has been modified, by providing a first VCXO as part of the integrated circuit, providing a second VCXO, adjusting one of the VCXOs in a first preselected manner, determining a first frequency count of the adjusted VCXO during a first preselected time interval using the other VCXO, adjusting the one of the VCXOs in a second preselected manner, determining a second frequency count of the adjusted VCXO during the first preselected time interval using the other VCXO, averaging the first and second frequency count to provide an average frequency count, adjusting the average frequency count in a predetermined manner, and comparing the adjusted average frequency count to a previously stored, determined, or provided average frequency count to determine if the environment of the integrated circuit has been modified.

Integrated circuit identification system

A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU),executes instructions from ROM,and accesses data from RAM,. Similarly, Arithmetic Unit (AU),executes instructions from ROM,and accesses data from RAM,. Both processor operate in parallel and exchange data by accessing RAM,. AU,can receive an instruction directive from BPU,directing it to perform a selected sequence of instructions in a loosely coupled manner. AU,can also receive an instruction directive from BPU,directing that a portion of AU,operationally replace a portion of BPU,for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.

Microprocessor with functional units that can be selectively coupled

A data processing device uses a portion of a random access memory as an input buffer for holding a portion of a stream of data which is being processed by a processing unit within the processing device. Various break-point source tasks,determine discontinuities in the portion of data stored in the input buffer and a sorted list of the addresses of the discontinuities is maintained in breakpoint queue,. Since the buffer is managed in a FIFO manner, a single breakpoint register,is sufficient to monitor addresses as they are provided by an address register,for accessing the random access memory. When a breakpoint is detected, the breakpoint queue and the breakpoint register is updated by an update task

A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Audio decoder circuit and method of operation

A data processing device is programmed to decode and transform a stream of data representing a plurality of subband encoded channels of audio data into one or more channels of PCM encoded data for reproduction by a speaker subsystem. An improved method for decoding and transforming utilizes downmix matrices (1021 and 1022) to form downmixed frequency domain channels in buffers (1031-1034). Only two long DCT transform operations (1041 and 1042) and two short DCT transform operations (1043 and 1044) are needed to transform the downmixed frequency domain channels into a left PCM output (1071) and a right PCM output (1072).

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Allen, TX, United States of America

Frank L Laczko, Sr