Vishay-siliconix

Siliconix Incorporated

Siliconix Taiwan Ltd

Siliconx (taiwan) Ltd.

Frank Kuo

Sen Mao

Mohammed Kasem

King Owyang

Suresh Belani

Sam Kuo

Oscar Ou

Kyle Terrill

Yuming Bai

Serge Jaunay

Peter Wang

Eddy Tjhia

Chang-Sheng Chen

Yehja Mohammed Kasem

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Method for fabricating stack die package

A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Dual lead frame semiconductor package and method of manufacture

In one embodiment, a stack die package can include a lead frame and a first die including a gate and a source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. The gate and source are flip chip coupled to the lead frame. The stack die package can include a second die including a gate and a drain that are located on a first surface of the second die and a source that is located on a second surface of the second die that is opposite the first surface. The source of the second die is facing the drain of the first die.

Stack die package

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Complete power management system implemented in a single surface mount package

An encapsulation technique for leadless semiconductor packages entails: (a) attaching a plurality of dice () to die pads in cavities (--) of a leadframe, the cavities arranged in a matrix of columns and rows; (b) electrically connecting the dice to a plurality of conducting portions (-) of the leadframe; and (c) longitudinally injecting molding material into the cavities along the columns via a plurality of longitudinal gates (--) of the leadframe to package the dice in the cavities, the longitudinal gates situated between the cavities along the columns.

Encapsulation techniques for leadless semiconductor packages

The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Semiconductor packages including die and L-shaped lead and method of manufacture

Encapsulation method for leadless semiconductor packages

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Growing community of inventors

Kaohsiung, Taiwan

Frank Kuo