Advanced Micro Devices Corporation

Globalfoundries Inc.

Frank Koschinsky

Bernd Hintze

Volker Kahlert

Matthias Lehr

Holger S Schuehrer

Eckhard Langer

Tobias Letz

Peter H&uuml;bler

Roland Jaeger

Frank Wagenbreth

Xunyuan Zhang

Frank Feustel

Thomas Werner

Joerg Hohage

Tibor Bolom

Moritz Andreas Meyer

Peter Huebler

Dirk Utess

Oliver M Witnik

Peter Hübler

Kun Ho Ahn

Heiko Weber

A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.

Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Methods for fabricating integrated circuits including barrier layers for interconnect structures

Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

Methods of forming metal nitride materials

A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean process

A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

Method for detecting defects in a diffusion barrier layer

For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters.

Multi-step deposition control

During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an 'optimized' manufacturing environment may be obtained on the basis of the test strategy disclosed herein.

Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices

A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

Method of testing an integrity of a material layer in a semiconductor structure

In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools.

Reduced wafer warpage in semiconductors by stress engineering in the metallization system

A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition

By forming a thin passivation layer after the formation of openings connecting to a highly reactive metal region, any queue time effects may be significantly reduced. Prior to the deposition of a barrier/adhesion layer, the passivation layer may be efficiently removed on the basis of a heat treatment so as to initiate material removal by evaporation.

Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layer

A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

Method for cleaning the surface of a substrate

The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.

Void formation monitoring in a damascene process

For determining the quality of interconnections in integrated circuits, especially in damascene applications, a method of monitoring voids is disclosed, wherein a barrier metal layer is directly deposited on a planarized metal to provide a large-area surface that is not required to be destroyed for further analysis of the interface between the metal and the barrier metal layer. The analysis may be carried out by employing an electron microscope operated in a back-scatter mode.

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Radebeul, Germany

Frank Koschinsky