Infineon Technologies Ag

Frank Klotz

Josef-Matthias Gantioler

Helmut Gassel

Leo Lorenz

Stephan Cordes

Martin M&auml;rz

J&uuml;rgen Petzoldt

Axel Rafoth

In some examples, a circuit is configured to generate a first signal based at least in part on an input signal, wherein the first signal comprises a common mode signal and a load signal. The circuit is further configured to generate a second signal based at least in part on the input signal, wherein the second signal comprises an inverted version of the common mode signal. The circuit is further configured to apply the first signal and the second signal to a load.

Active common mode cancellation

A voltage stabilization circuit is configured between two signal lines. Each of the signal lines carries a signal, and an interference signal is superimposed on at least one of the signals. The voltage stabilization circuit includes an amplifier circuit that provides an anti-phase signal obtained as an amplified difference between the interference signal and a reference signal. The anti-phase signal has a phase that is opposite the phase of the interference signal. The configuration further includes a matching circuit, which is connected in series with the amplifier circuit, and which generates a compensation signal from the anti-phase signal and superimposes the compensation signal on the signal that is superimposed with the interference signal.

Circuit configuration for voltage stabilization

The power switch has considerably reduced common-mode interference and relatively reduced circuit complexity. The power switch is formed of a semiconductor chip on a leadframe. A first terminal of the semiconductor chip is connected to the active potential and a second terminal for inactive potential is connected to the leadframe. The second terminal is either the drain of a transistor or the anode of a diode.

EMC-optimized power switch

A power semiconductor array on a direct copper bonding (DCB) semiconductor substrate is created, in which the interference emissions propagated via its terminal lines are eliminated, or at least greatly reduced, directly on the semiconductor device. The power semiconductor array on the DCB substrate includes a first intermediate circuit terminal connected to a positive potential, a second intermediate circuit terminal connected to a negative potential, and at least one load terminal. The power semiconductor array further includes at least two power switches for connecting the load terminal to the first and second intermediate circuit terminals in alternation. The power semiconductor array is characterized by bridging connections that connect at least some of the terminals of the power semiconductor array that lead to the outside to one another in pairs, so that interference circuits within the power semiconductor array are closed.

Growing community of inventors

München, Germany

Frank Klotz