Arm Limited

Arm Norway as

Fxi Technologies as

Frank Klaeboe Langtind

Andreas Due Engh-Halstvedt

Jorn Nystad

Borgar Ljosland

Mario Blazevic

Edvard Sorgard

Daren Croxford

Jørn Nystad

Sandeep Kakarlapudi

Mark Underwood

Rafal Stepuch

Remi Pedersen

Olof Henrik Uhrenholt

Edvard Sørgård

Philip Carlos Garcia

Michael Martin Klock

Tord Kvestad Øygard

Joe D Tapply

Daniel Fedai Larsen

Wei Shao

Peter Anthony Hearne

Naveen Kumar Singh

Shareef Justin Jalloq

When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed, vertex attribute processing is performed for vertices of assembled primitives to generate one or more processed vertex attributes for vertices of the assembled primitives. Processed vertex attributes for vertices of assembled primitives are stored in a first storage, and additionally in a second storage. Then when obtaining processed vertex attributes for an assembled primitive, it is checked whether processed vertex attributes for the vertices of the primitive are present in the second storage, and when they are, the processed vertex attributes are read from the second storage, but when the processed vertex attributes are not in the second storage, they are read from the first storage instead.

Graphics processing systems for handling vertex attributes

A method of operating a graphics processor to process sets of geometry to generate an output. Each set of geometry is associated with lower level geometry including vertex data to be used when rendering the geometry as well a separate higher level representation of the geometry. The higher level representations of the geometry can be obtained by the graphics processor independently of the other, lower level geometry and used to determine which sets of geometry should be processed for which regions of the output. Once this determination is made, the regions can be rendered by obtaining and processing the lower level geometry accordingly.

Graphics processing systems

The present disclosure relates to tile-based rendering systems. In particular comprises a method for encoding primitive metadata into a primitive list in which a primitive metadata command is included into the primitive list that is able to indicate types of primitive metadata from a set of different types of primitive metadata that can be indicated by the primitive metadata command are included into the primitive list in association with the primitive metadata command. The indicated primitive metadata can then be included in the primitive list following the primitive metadata command. Corresponding primitive list formats and graphics processing systems using such primitive metadata command are also disclosed.

Graphics processing methods and systems for encoding primitive metadata

The present disclosure relates to tile-based rendering systems. In particular there is provided a new primitive list format in which a sequence of commands generated for the primitive list includes a number of different respective types of commands including 'primitive' type commands storing primitive data, ‘state’ type commands storing state data and ‘configuration’ type commands for storing configuration data, wherein the primitive, state and configuration data can accordingly be stored separately in the primitive list, using the different respective types of commands. Also disclosed are techniques for encoding the data into the respective different types of commands.

Graphics processing

When performing tile-based graphics processing, a first vertex shading operation to generate vertex shaded position data for vertices is performed, and the vertex shaded position data used to prepare primitive lists indicating which primitives should be rendered for respective rendering tiles. Then, when processing a tile, a second vertex shading operation is performed for vertices of primitives for the tile for which fragments have been generated by a rasteriser prior to rendering the graphics fragments, to generate vertex shaded non-position attribute data for the vertices, based on the results of early depth testing before the fragments are rendered.

A method of processing data in a graphics processor when performing tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering. The rendering is performed as two separate processing passes: a first processing pass that sorts primitives into respective regions of the render output and a second processing pass that renders the tiles into which the render output is sub-divided for rendering. During the first processing pass, 'tile elimination' data is generated indicative of which of the rendering tiles should be rendered during the second processing pass. The tile elimination data generated in the first processing pass can then be used to control the rendering of tiles during the second processing pass.

Graphics processors

Disclosed subject matter relates generally to graphics processing, and relates more particularly to processing graphics vertex content.

System, devices and/or processes for graphics vertex processing

When generating a graphics processing output, a sequence of one or more of primitives to be processed when generating the output is assembled from a set of vertex indices provided for the output based on primitive configuration information provided for the output, each assembled primitive of the sequence of assembled primitives comprising an identifier for the primitive and a set of one or more vertex indices for the primitive. One or more attributes for vertices of the assembled primitives are then shaded and fetched based on the vertex indices of the assembled primitives. The assembled primitives including their shaded fetched vertex attribute(s) are then provided to later stages of the graphics processing pipeline for processing.

Primitive assembly and vertex shading of vertex attributes in graphics processing systems

A method of operating a graphics processor that executes a graphics processing pipeline comprising a vertex shading stage is disclosed. A set of blocks of memory space that may be represented by a linked list is provided and memory space for storing vertex shaded attribute data generated by the vertex shading stage is allocated from one of the blocks of memory space in the set of blocks of memory space. When data stored in a block of memory space is no longer needed by the graphics processing pipeline, the block can be 'recycled' for use by the pipeline.

A method of operating a graphics processor that is configured to execute a graphics processing pipeline is provided. The method comprises the graphics processor reading, from an index buffer in external memory, a block of data comprising plural sets of indices, each set of indices comprising a sequence of indices indexing a set of vertices that defines a primitive of a plurality of primitives to be processed by the graphics processing pipeline. The graphics processor compresses the block of data to form a compressed version of the block of data, and stores the compressed version of the block of data in an internal memory of the graphics processor.

Index buffers in graphics processing systems

A scene to be rendered is divided into plural individual sub-regions or tiles. The individual sub-regionsare also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set of 8&#xd7;8 sub-regions which encompasses the entire scene area. There is then a group of four 4&#xd7;4 sets of sub-regions, then a group of sixteen 2&#xd7;2 sets of sub-regions, and finally a layer comprising the 64 single sub-regions. A primitive list building processor takes each primitive in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions and the locations of the sets of sub-regions, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.

Method of and apparatus for processing graphics

A graphics processing pipeline includes: a position shader, a tiler, a pool of memory for storing primitive lists and vertex shaded attributes data for vertices, a varying-only vertex shader, and a fragment frontend and shader. The position shader performs vertex shading for the positional attributes of the vertices of a set of vertices to be processed by the graphics processing pipeline. The tiler uses the vertex shaded position data to identify primitives that should be processed further to generate the render output. When the tiler determines that a vertex should be processed further to generate the render output, it allocates memory space in the memory pool for storing vertex shaded attributes data for the vertex. Vertex shaded attributes data for the vertex is then stored in the allocated space in the memory pool for later use, e.g., by the fragment frontend and shader.

A tile-based graphics processing pipeline includes a back-facing determination and culling unit that is operable to cull back-facing triangles before the tiling stage. The back-facing determination and culling unit include a triangle size estimator that estimates the size of a triangle being considered. If the size of the triangle is less than a selected size, then the area of the triangle is calculated using fixed point arithmetic and the result of that area calculation is used by a back-face culling unit to determine whether to cull the triangle or not. On the other hand, if the size estimator determines that the primitive is greater than the selected size, then the triangle bypasses the fixed point area calculation and back-face culling unit and is instead passed directly to the tiler.

When writing data to memory via a write buffer including a write cache containing a plurality of lines for storing data to be written to memory and an address-translation cache that stores a list of virtual address to physical address translations, a record of a set of lines of the write cache that are available to be evicted to the memory is maintained, and the evictable lines in the record of evictable lines are processed by requesting from the address-translation cache a respective physical address for each virtual address associated with an evictable line. The address-translation cache returns a hit or a miss status to the write buffer for each evictable line that is checked, and the write buffer writes out to memory at least one of the evictable lines for which a hit status was returned.

Growing community of inventors

Melhus, Norway

Frank Klaeboe Langtind