Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Other

Frank Kelsey Baker, Jr

Mehul D Shroff

Mark Douglas Hall

Perry H Pelley

Cheong Min Hong

Erwin J Prinz

Ravindraraj Ramaraju

Anirban Roy

Feng Zhou

Ko-Min Chang

Thomas Jew

Ross Sinclair Scouller

Jon D Cheek

Gowrishankar L Chindalore

Michael Alan Sadd

Craig T Swift

Alexander Hoefler

Paul A Ingersoll

Venkatagiri Chandrasekaran

Marius K Orlowski

James David Burnett

Bruce L Morton

Jane A Yater

Howard C Kirsch

Chen He

Anis Mahmoud Jarrar

Fuchen Mu

Ronald J Syzdek

Yasunobu Kosa

Sucharita Madhukar

Juan Buxo

Daniel L Andre

Stephen F McGinty

Thomas F McNelly

Danny P Shum

Wei-Ming Chen

Kevin Yun-kang Wu

Mohammed Suhail

Sung-Wei Lin

Gregory M Yeric

A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.

Memory reads of weight values

A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.

NVM architecture with OTA support

The motion detector alert device comprises a detector unit and an annunciator unit. The detector unit comprises a threaded base and a threaded socket. The threaded base of the detector unit screws into a motion sensing light fixture in place of the bulb. The bulb screws into the threaded socket. The detector unit monitors electrical energy passing from the motion sensing light fixture to the bulb and transmits a signal when the light fixture energizes the bulb. The annunciator unit may be located inside of a building. Responsive to reception of the signal sent from the detector unit, the annunciator unit may produce an audible sound to alert occupants of the building that motion has been sensed outside.

Motion detector alert device

A non-volatile memory includes a first bit cell having a programmable resistive element coupled to a write bit line wherein the programmable resistive element is programmable to one of two resistive states, a resistive element coupled to the programmable resistive element at a circuit node, and a first transistor configured to operate in saturation during a read operation. The first transistor has a control electrode coupled to the circuit node and a first current electrode coupled to a read bit line.

Memory with read circuitry and method of operating

A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.

Non-volatile memory using bi-directional resistive elements

A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.

A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.

A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.

Non-volatile static random access memory (NVSRAM) having a shared port

A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.

Magnetic random access memory (MRAM) and method of operation

A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. A first bi-directional resistive element has a cathode coupled to the second current electrode of the first select transistor and an anode coupled to an internal node. A second bi-directional resistive element has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor. A third transistor has a first current electrode coupled to a third bit line, a second current electrode coupled to the internal node, and a control electrode coupled to a word line.

Pseudo SRAM using resistive elements for non-volatile storage

A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

A memory cell includes a bi-directional resistive memory element, a first transistor, and a capacitive element. The bi-directional resistive memory element has a first terminal directly connected to a first power rail and a second terminal coupled to an internal node. The first transistor has a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to one of the first power rail, a second power rail, or a read wordline. The capacitive element includes a first terminal coupled to the internal node and a second terminal coupled to the read wordline.

Non-volatile memory using bi-directional resistive elements and capacitive elements

A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells () prior to the formation of high-k metal gate electrodes for CMOS transistors () using a planarized dielectric layer () and protective mask () to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Embedded NVM in a HKMG process

A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.

Growing community of inventors

Austin, TX, United States of America

Frank Kelsey Baker, Jr