Texas Instruments Corporation

Frank J Sweeney

Honglin Guo

Apparajan Ganesan

An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

Contaminant collection on SOI

A frequency compensated current output circuit with increased gain. The current output circuit is an improved current mirror where the gate of an output transistor (MP06) is coupled to an impedance (Ra) located in the conductive path of the mirror transistor (MP05), so that the current flowing out of the circuit is increased by an amount proportional to the resistive value of the impedance (Ra). The circuit includes a frequency compensation network (Rc, Cc) to offset the gain peaking effects which occur in the frequency response of the circuit due to the gain impedance. An output amplifier is described using the current output circuit. Other embodiments are described.

Frequency compensated current output circuit with increased gain

A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130). In one embodiment (120), the MOS state controlling transistor (124) is an NMOS transistor and the MOS logic transistor (122) is a PMOS transistor.

Circuit and method for providing a known logic state at insufficient

A method of fabricating a resistor which comprises the steps of providing a semiconductor substrate, preferably silicon, forming a layer of oxide over the substrate, providing on the layer of oxide a region of material having a substantially higher resistance in the undoped state than in the doped state, preferably polysilicon, patterning a region over the material to expose predetermined regions of the material, doping the exposed regions of the material to a predetermined doping level substantially greater than the doping level of the original material, masking the doped regions and a portion of the previously unexposed regions of the material on spaced apart portions of the doped regions and etching away the exposed region of material external to the doped regions and external to the portion of the previously unexposed regions of the material on spaced apart portions of the doped regions.

Method of fabricating precisely matched polysilicon resistors

A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programmning the device's logic array (22).

Growing community of inventors

Rowlett, TX, United States of America

Frank J Sweeney