Intermec IP Corporation

Witricity Corporation

Frank J Pergal

Marin Soljacic

Morris P Kesler

Katherine L Hall

Andre B Kurs

Aristeidis Karalis

Andrew J Campanella

Konrad J Kulikowski

David A Schatz

Eric R Giler

Ron Fiorello

Alan F Jovanovich

Bruce G Warren

Qiang Li

A delay diversity processor for use in receiving direct sequence spread spectrum data utilizes multipath signals to enhance bit synchronization performance by integrating the magnitude of each multipath signal to allow for erratic fluctuations in the multipath signal. As a result, the receiver is less prone to sudden signal strength variation that might trigger erroneous bit resynchronization. The delay diversity processor comprises a first circuit which determines a magnitude value for each of a plurality of correlated signal samples of individual data bits of plural data streams of the received spread spectrum data. A second circuit integrates each of the magnitude values over a period of time corresponding to receipt of a plurality of the individual data bits. The integrated magnitude values provide a measure of confidence of a particular one of the correlated signal samples with respect to remaining ones of the correlated signal samples. The correlated signal sample having the most consistently high measure of confidence is thus most likely to contain reliable and valid data. In an embodiment of the delay diversity processor, the digital delay circuit of the second circuit provides for resetting of the integrated magnitude values within following interruption of receipt of the spread spectrum data. The data values within the digital delay circuit can be reset either to zero, or to a predetermined value. The use of a predetermined value improves the ability of the delay diversity processor to generate valid data following an interruption of the spread spectrum data.

Methodology for received signal enhancement utilizing delay diversity

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Los Angeles, CA, United States of America

Frank J Pergal