Motorola Corporation

Frank J Juskey

Douglas W Hendricks

Jonathon G Greenwood

Bruce J Freyman

Robert Thomas Carson

Marc V Papageorge

Kenneth M Wasko

Arnold W Hogrefe

John R Thome

Scott Joslin

An electronic assembly (10) comprises one or more electronic components (18) having solder terminations (20), and a printed circuit substrate (12) having printed circuit traces (14, 16), wherein at least one of the solder terminations of the one or more electronic components (18) and the printed circuit traces (14, 16) of the printed circuit substrate (12) has a secondary finish produced by application of an electrolessly deposited nickel film (26) containing phosphorus which is further plated with gold (28). An indium-tin-lead solder paste (22) is utilized in a soldering process to attached the one or more electronics components (18) to the printed circuit traces (14,16) on the printed circuit board (12), such that the indium-tin-lead solder (22) provides improved solder joint integrity with the secondary finish. The electronic components (18) include semiconductor devices such as ball grid arrays (1000) and flip-chip integrated circuits (1010).

Electronic assembly

A display module (207) is used that integrates circuit components (402-422) thereto. The display module (207) includes a displayable element (101), and a first conductive runner (206) located on a backside of the display module (207) that couples to the displayable element (101). Additionally, display module (207) includes at least one layer of substrate material (208, 210) covering the backside of the display module (207) with a portion of the first conductive runner (206) exposed, and a first conductive coupling element (212, 302) coupled to the portion of the first conductive runner (206).

Selective call receiver having a display module with integrated circuits

A novel process for plating a substrate without solder mask wherein the substrate is coated with a polymer catalyst to assist adhesion of conductive metal to the substrate. Next, a first plating mask photopolymer, or plating resist, is coated over the polymer catalyst, a circuit pattern is imaged onto the first plating mask and the first plating mask is developed to reveal windows, or circuit traces, in the first plating mask corresponding to the circuit pattern to be embodied on the substrate. Thereafter, a first conductive material such as copper is plated into the windows, and, thereafter, a second conductive material such as nickel may be plated into the windows on top of the first conductive material. Then, the first plating mask is removed from the substrate, leaving behind the conductive material in the form of the desired circuit pattern. Next, a second plating mask photopolymer is formed over the substrate and conductive materials, and an I/O interconnect mask corresponding to the I/O interconnect pads is photo-optically imaged onto the second plating mask and the second plating mask is developed to remove portions thereof, creating 'interconnect voids,' corresponding to the interconnect pads. Thereafter, a third conductive material such as gold is plated into the interconnect voids to create conductive I/O pads.

Method for plating a substrate to eliminate the use of a solder mask

A method of producing multi-layered chip carriers by coating the surface of a base layer with a photosensitive dielectric material which forms a dielectric layer; curing at least a portion of the dielectric layer by exposure to radiation; depositing a catalyst on the cured portion of the dielectric layer to form a sensitized dielectric layer; applying a photoresist layer upon the sensitized dielectric layer; curing at least a portion of the photoresist layer; developing the cured photoresist layer by removing uncured portions, thereby exposing corresponding portions of the underlying sensitized dielectric layer; forming conductors on the exposed dielectric layer; stripping the cured photoresist layer: coating a layer of photosensitive dielectric material upon the cured dielectric layer; and repeating the steps to produce successive layers which form a multi-layer chip carrier having a plurality of conductor layers separated by layers of insulating dielectric material.

Method for producing high density multi-layer integrated circuit carriers

A method of interconnecting circuit modules (30) to mother boards (50) each having a plurality of mating solder pads (32, 52) is available. The solder pads (32, 52) have respective pairs of arms (40, 42) and (54, 56) with a venting channel (36, 58) formed between each pair of arms to vent solder medium when the solder pads are reflowed to interconnect the circuit modules and mother boards.

Method and structure for attaching a circuit module to a circuit board

A wire bond pad arrangement (104) has an improved pad density for providing a plurality of wire bond terminations for interconnection with corresponding terminations (604) of an IC chip (302. The wire bond pad arrangement (104) includes a substrate (102) and a plurality of pads (912) disposed on the substrate (102) adjacent to one another to form a row of pads (912). Each of the pads (912) is formed in a trapezoidal shape having short and long sides parallel to one another and substantially perpendicular to a line from a central point of the pad (912) to a central point of the corresponding termination (604) of the IC chip (302). The long sides of adjacent pads (912) are positioned alternately towards and away from the corresponding terminations (604) of the IC chip 302).

Wire bond pad arrangement having improved pad density

An integrated circuit package includes a stacked integrated circuit chip arrangement (140) placed on a circuit substrate. The stacked IC chip arrangement includes a first IC chip (110) and a second IC chip (120), each having an array of terminals (116, 126) and being positioned in a face-to-face manner. An interposed substrate (130) is positioned between the first IC chip (110) and the second IC chip (120) such that circuitry disposed on the interposed substrate (130) provides electrical connection among the arrays of terminals of the first IC chip (110) and the second IC chip (120) and external circuitry.

Integrated circuit package having a face-to-face IC chip arrangement

A method and apparatus for use in forming pre-positioned solder bumps (104) on a pad arrangement (100) of a substrate (101) include placing a predetermined pattern (306) of solder preforms (304) in contact with a meltable adhesive fluxing agent (302) on a carrier tape (402), and then heating the fluxing agent (302) to melt it. Next, the fluxing agent (302) is cooled to resolidify it, thereby securing the solder preforms (304) to the carrier tape (402). The carrier tape (402) is then aligned over the pad arrangement (100) and the solder preforms (304) are transferred to the pad arrangement (100) by heating the solder preforms (304) to form the solder bumps (104) in the predetermined pattern (306).

Growing community of inventors

Coral Spring, FL, United States of America

Frank J Juskey