C-cube Microsystems, Inc.

Other

Frank H Liao

Stephen C Purcell

David E Galbi

Yvonne C Tse

A microwave anti-heat supporter for a piece of food to be heated by microwave includes a heating platform, a plurality of supporting legs, and a heating arrangement. The heating platform has an upper supporting surface for the food resting thereon, and a lower ventilating surface. The supporting legs downwardly extend from the ventilating surface of the heating platform to raise up the supporting surface of the heating platform in a suspended manner. The heating arrangement contains a plurality of through ventilating slots spacedly formed on the heating platform to communicate the supporting surface with the ventilating surface, in such a manner that the ventilating slots are adapted for allowing the microwave to circulate from the ventilating surface to the supporting surface so as to effectively generate a uniform heat applying at the food on the heating platform at all directions.

Microwave anti-heat supporter

A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920.times.1080 pixel display space is divided into four vertical sections of 480.times.1080 pixels. Each memory bank stores the values of pixels in one non-overlapping group of 240.times.1080 pixels. Each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas. The video decompression structures decode the vertical sections in lock-step to avoid the problem of the same bank of memory being accessed by more than one video decompression structure. In one embodiment of the present invention, a macroblock fetch can cross 1-4 DRAM page boundaries. So, in order to maintain the lock-step relationship of the video decompression structures, each page mode access is limited to fetching only an 8.times.8 quad pixel picture area, so that regardless of the number of DRAM page boundaries required to be crossed, four page mode access cycles are required for each reference macroblock fetched.

Decompression processor for video applications

A motion compensation structure and a method are provided for decoding interframe coded video data using motion vectors. The motion compensation structure includes a filter for resampling the pixel data in both vertical and horizontal directions, a prediction memory structure and a weighted adder structure. In one embodiment of the present invention, a weighted adder structure and a method are provided for performing bilinear interpolation of two values using multiplexers and an multiple-input adder.

A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel.times.2 pixel 'quad pixel' configuration, or in a 4 pixel.times.1 pixel horizontal 'scan' configuration. In addition, a structure and a method are provided for accessing a 16.times.16-pixel picture area in two parts, in order that the number of DRAM page boundaries crossed during access of the 16.times.16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs.

Method and apparatus for mapping data of a 2-dimensional space from a

A method and a structure are provided to decode intra-frame and interframe coded compressed video data. In one embodiment of the present invention, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure in accordance with the present invention communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor in the decompression structure of the present invention provides overall control to the decoder, IDCT and motion compensation coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the decoder, the IDCT and the motion compensation coprocessors.

MPEG video decompression processor

A method and a structure are provided to decode intraframe and interframe coded compressed video data. In one embodiment, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosine transform coprocessor and a motion compensation coprocessor communicate. The decompression structure communicates with a host computer over a host bus and with an external dynamic random access memory over a memory bus. The processor provides overall control to the coprocessors by reading and writing into a plurality of data and control registers, each register associated with one of the coprocessors. A structure including four of the decompression structures and a method are provided for decoding high definition television (HDTV) signals. In this structure for decoding HDTV signals, each decompression structure decodes a 480.times.1088-pixel picture area with access to up to two additional 240.times.1088-pixel picture areas.

Growing community of inventors

Sunnyvale, CA, United States of America

Frank H Liao