Intel Corporation

Frank E LeClerg

Orville H Christeson

Jerald N Hall

Sean R Babcock

Frank L Wildgrube

Mike Kinion

John Yuratovac

Frank Binns

David J O'Shea

Larry D Aaron, Jr

Bruce C Edmonds, Jr

Craig W Keating

Pete D Vogt

Scott M Rider

Peter D Vogt

A memory system includes multiple memory modules, which communicate with a memory controller over one or more channels. When a memory module receives an initialization command from a processor or the memory controller, the memory module performs an initialization procedure of the memory locations associated with the memory module. In an embodiment, at least a portion of the initialization procedure is performed in parallel with the other memory modules performing initialization procedures. Each memory module may include a buffer module, which receives the initialization command, and generates and sends data packets with the initialization data to the memory locations. A memory module also can receive a test command from the processor or memory controller, which causes the memory module to read data from the memory locations, compare that data with expected data, and keep track of any errors that may occur.

Distributed memory initialization and test methods and apparatus

The present disclosure relates to resource management of memory using information regarding the physical state of the memory device(s), and, more specifically, to attempting to reduce the heat dissipation of a memory device by managing the contents of the memory device.

Thermal memory control

A thermal management that redirects the target of read transactions from a thermally failed Dual Inline Memory Module (DIMM) in one mirror, to the corresponding DIMM in the other mirror. The memory controller or MCH would effectively bias the read transactions toward the mirror that is best able to respond based on thermal feedback. Likewise, this may be used as a temporary redirection that continues for only as long as was required to reduce the operating temperature in the failing DIMM.

Method, apparatus, and system for memory read transaction biasing in mirrored mode to provide thermal management

A method of electing a bootstrap processor from among a plurality of processor includes creating an atomic access shared location and electing one of said processors as the bootstrap processor.

Bootstrap processor election mechanism on multiple cluster bus systems

A system to initialize a memory device. An operating system executes an application program. A memory device has a plurality of memory addresses that hold data. A firmware device holds settings for the memory device and sends a completion signal to the operating system only after an initialization of the memory device has been completed in response to an initialization request being received from the operating system. A memory controller initializes a range of the memory addresses to a configurable value after receiving the initialization request from the firmware device, and sends the completion signal to the firmware device after the initialization is completed.

Method and apparatus providing an interface to allow physical memory to be initialized using firmware/hardware methods

Bootstrap processor election mechanism on multiple cluster bus system

An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.

Method and apparatus for setting the operating parameters of a computer system

An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.

Growing community of inventors

Portland, OR, United States of America

Frank E LeClerg