Arm Limited

Freescale Semiconductors Inc.

Frank David Frederick

Richard Slobodnik

Andy Wangkun Chen

Teresa Louise McLaurin

Yew Keong Chong

Cyrille Nicolas Dray

Paul Stanley Hughes

Thomas K Johnston

Yannis Jallamion-Grive

Kartikey Jani

Brandon Michael Backlund

Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.

Latch circuitry for memory applications

Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

Memory testing techniques

A memory circuit includes input multiplexers passing one of a pair of input bits. A first input multiplexer receives a first data bit and a serial input bit. Additional input multiplexers receive either a respective pair of data (D) bits, or a write-enable (WEN) bit and a single D bit. Scan latches receive one of the input bits and provide a scan output bit. OR gates arranged receive the scan output bit from a different scan latch, and perform a logical OR operation thereon to generate an OR output bit. Downstream output multiplexers pass a corresponding bit from a bit array or the OR output bit from a corresponding OR gate, and sense latches receive the corresponding bit from one of the output multiplexers and provide a sense output bit. Each sense output bit feeds into one or more input multiplexers when a bit-write-mask function is disabled.

Memory embedded full scan for latent defects

Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

Scan cell for dual port memory applications

A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.

Method and apparatus for memory self testing

A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test mode, said processor clock control device comprising: a clock signal input operable to receive a slower reference clock signal or a higher speed operational clock signal; at least two clock signal outputs each operable to output a clock signal to a respective domain of said processor; a mode control signal input operable to receive a mode control signal indicating a mode of operation of said processor; a launch control signal input operable to receive a launch control signal, said launch control signal indicating portions of said processor to be tested; and an initiation signal input operable to receive an initiation signal indicating initiation of a processor test; wherein said processor clock control device is operable: in response to receipt of a test mode signal at said mode control signal input to receive a reference clock at said clock signal input and to output said reference clock at at least one of said plurality of clock signal outputs; and in response to a predetermined launch control signal received at said launch control signal input, said predetermined launch control signal indicating testing of a path between one of said clocked domains clocked by one of said clock signal outputs and one other of said clocked domains clocked by one other of said clock signal outputs, and following receipt of said initiation signal, to independently control said plurality of clock signal outputs such that at least one launch clock pulse is output from said one of said clock signal outputs while said one other of said clock signal outputs is suppressed, and following this to output at least one capture clock pulse from said one other of said clock signal outputs while said one of said plurality of clock signal outputs is suppressed.

Clock control of a multiple clock domain data processor

An integrated circuit and method for testing memory on that integrated circuit includes processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided for executing test events in order to seek to detect any memory defects in the number of memory units. The controller includes a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the controller is then operable, following the single programming operation, to execute the sequence of test events.

Integrated circuit and method for testing memory on the integrated circuit

In order to test the memory access signal connections between a data processing circuit, such as a processor core, and a memory, a subset of memory access signal connectionsare provided with associated scan chain cellsso that they may be directly tested. The remainder memory access signal connectionswhich are common to all the expected configurations of the memoryare tested by being driven by the processor coreitself with data being passed through the memory and captured back within the processor corefor checking.

Testing memory access signal connections

Embodiments of the present invention relate generally to scan clock waveform generation. One embodiment utilizes global and local circular shift registers to provide a series of shift/capture pulses at a manageable frequency for the tester and launch pulses that are phase shifted in order to provide for at-speed testing. Therefore, scan test patterns may be shifted in or out of state elements at lower frequencies as compared to the normal operating frequency of the integrated circuit being tested, while still allowing for at-speed testing. An alternate embodiment utilizes a circular shift register in combination with static storage devices and waveform generators to provide the shift/capture pulses and launch pulses. Embodiments of the present invention also allow for clock inversion where the clock and clock bar signals are dependent during normal mode and independent during scan test mode.

Growing community of inventors

Austin, TX, United States of America

Frank David Frederick