International Business Machines Corporation

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Qimonda Ag

Frank David Ferraiolo

Daniel Mark Dreps

Kevin Charles Gower

Robert J Reese

Anand Haridass

John E Gersbach

Robert S Capowski

Daniel Francis Casper

Prasanna Jayaraman

Ilya I Novof

Paul William Coteus

Charles Joseph Masenas

Marten J Halma

Michael B Spear

Timothy O Dickson

Albert Manhee Chu

Mark William Kellogg

Wiren Dale Becker

Michael Sperling

Bradley David McCredie

Joseph M Hoke

Roger A Rippens

Richard C Jordan

Gary Alan Peterson

Thomas Anthony Gregg

Michael Stephen Floyd

Martin L Schmatz

Peilin Song

Douglas James Joseph

Samir Kirit Patel

Anuja Sehgal

Ravi Kumar Arimilli

Patrick James Meaney

Steven Michael Douskey

Kenneth Lee Wright

Kevin Franklin Reick

David John Krolak

Derrick LeRoy Garmire

Christine M Desnoyers

Jonathan Yang Chen

Robert Frederick Stucke

Edward J Nowak

John Steven Dodson

Warren Edward Maule

John Atkinson Fifield

Luis Alfonso Lastras-Montano

James Stephen Fields, Jr

Daniel Joseph Friedman

Kyu-hyoun Kim

Ashish Jagmohan

Todd Edward Takken

Michele M Franceschini

Timothy Jay Dell

Pak-kin Mak

Robert Brett Tremaine

John Francis Bulzacchelli

Eric Eugene Retter

Norman Jay Rohrer

Steven Frederick Oakland

James T Brady

Daniel Lawrence Stasiak

Tobias Webel

Michael Raymond Trombley

Steven John Baumgartner

Glen Arthur Wiedemeier

Seongwon Kim

Tin-Chee Lo

Hubert Harrer

Robert Russell Williams

Gerard Vincent Kopcsay

Kevin W Kark

Paul William Rudrud

Norman Karl James

Roland A Bechade

Peter L Buchmann

Susan M Eickhoff

Martin W Sachs

Curtis Walter Preuss

William Richard Kelly

Roger Paul Gregor

Ulrich Weiss

Peter Matthew Thomsen

Jean-Marc Dortu

Allan Robert Bertolet

Masayuki Hayashi

Thomas M Cowell

Robert E Murray

David Peter Pagnani

Hector Saenz

Ching-Lung L Tong

Frank LaPietra

Toru Kobayashi

William J Scarpero, Jr

Kenneth J Shaw

Samuel K Weinstein

Daniel John Kolor

Glenn E Holmes

Leon Skarshinski

Haluk O Askin

A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Efficient calibration of a low power parallel data communications channel

A communications technique using spare bit-lanes to communicate changes in interface physical link layer bandwidth and/or active width provides for dynamic adjustment of power consumption of interface links without requiring a separate control path for exchanging the change information. One or more spare bit-lanes are used to communicate an indication of the operating frequency/active width change to the physical link layer of the remote side of the interface and an acknowledgement is sent back to provide complete handshaking of the operating characteristic change. The method can determine whether or not a spare bit-lane is available and prevent making the change if a spare bit-lane is not available until the interface is repaired and a spare bit-lane can then be used for communicating operating changes in operating frequency/active width.

System interconnect dynamic scaling handshake using spare bit-lane

Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units have dynamically adjustable bandwidth provided by an adjustable width and adjustable operating frequency. The bandwidths may be dynamically adjusted by predicting interface bandwidth requirements. From a required bandwidth, an active width and an operating frequency for the physical link layers are determined and set. The interface is operated according to the determined width and operating frequency.

System interconnect dynamic scaling by lane width and operating frequency balancing

A bus interface selects bit-lanes to allocate as spares by testing the performance margins of individual bit-lanes during initialization or calibration of the bus interface. The performance margins of the individual bit-lanes are evaluated as the operating frequency of the interface is increased until a number of remaining bit-lanes that meet specified performance margins is equal to the required width of the interface. The bit-lanes that do not meet the required performance margins are allocated as spares and the interface can be operated at the highest evaluated operating frequency. When an operating bit-lane fails, one of the spare bit-lanes is allocated as a replacement bit-lane and the interface operating frequency is reduced to a frequency at which the new set of operating bit-lanes meets the performance margins. The operating frequency of the interface can be dynamically increased and decreased during operation and the performance margins evaluated to optimize performance.

Bus interface optimization by selecting bit-lanes having best performance margins

An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.

Configurable differential to single ended IO

Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface controller detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The interface controller predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.

System interconnect dynamic scaling by predicting I/O requirements

Interface management techniques provide reduced power consumption along with reducing heat and EMI generation in a computer system having multiple interconnected processing units. Physical link layers of external interfaces that interconnect the processing units of have dynamically adjustable bandwidth and the bandwidths are dynamically adjusted by predicting interface bandwidth requirements. An interface control method detects events other than I/O requests that occur in a processing unit that are indicators of potential future transactions on one of the external interfaces connected to the processing unit. The method predicts, from the detected events, that future transactions will likely occur on the interface, and in response, controls the dynamically adjustable bandwidth of physical link layer of the interface to accommodate the future transactions.

A communications parallel bus receiver interface having N data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. An input switching network is configured to receive and couple N parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two adjacent bit receivers. A calibration device calibrates one of the two adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through each of N+1 receivers to periodically recalibrate each receiver (one at a time) while N inputs are processed continuously and uninterrupted. The interface is configured such that another receiver is receiving the same data as the receiver that is being calibrated, and the qualifications for receiver calibration can be made with minimal circuit overhead.

Parallel receiver interface with receiver redundancy

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Low latency data transfer between clock domains operated in various synchronization modes

A communications link includes multiple continuously calibrated parallel lines, wherein one or more lines are at least partially powered down while being continuously calibrated to reduce power consumption. In one aspect, at least N+1 lines (where N is the logical bus width) are periodically recalibrated, and at least one redundant line is powered down between calibrations. The redundant line could be either a true spare available for use as a replacement, or an extra line which carries functional data while other lines are being calibrated in turn. In another aspect, the logical bus width is variable, but does not exceed N. When N&#x3c;N, lines not carrying functional data are partially powered down between calibrations.

Parallel data communications mechanism having reduced power continuously calibrated lines

A communications parallel bus receiver interface having N+1 data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. One of the N+1 data signals comprising a spare data signal when a failure occurs in a corresponding channel transmitting one of N parallel data signals. An input switching network is configured to receive and couple N+1 parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two or three adjacent bit receivers. A calibration device calibrates one of the two or three adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through N+1 receivers for periodic recalibration of each receiver (one at a time) while N+1 inputs are processed continuously and uninterrupted.

Fault tolerant parallel receiver interface with receiver redundancy

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New Windsor, NY, United States of America

Frank David Ferraiolo