Intel Corporation

Frank Binns

Bret L Toll

Scott Dion Rodgers

James S Coke

Peter J Ruscito

David B Jackson

Masood Tahir

Ves A Naydenov

Mohan J Kumar

Mahesh S Natu

Rajesh S Parthasarathy

Stephen H Gunther

Robert Charles Swanson

Edward Allyn Burton

Linda J Rankin

Douglas M Carmean

Keshavan K Tiruvallur

Baskaran Ganesan

Shamanna M Datta

Thanunathan Rangarajan

Jack D Pippin

Gautam Doshi

John M Bauer

Rajesh Nagaraja Murthy

Robert J Greiner

Matthew C Merten

Bryant E Bigbee

David Lawrence Hill

David J O'Shea

Mayank Bomb

Frank E LeClerg

Larry D Aaron, Jr

Bruce C Edmonds, Jr

Craig W Keating

Jason W Brandt

Martin Guy Dixon

Andrew F Glew

David I Poisner

Shreekant S Thakkar

Nitin V Sarangdhar

William W Macy, Jr

David B Papworth

Shivnandan D Kaushik

David A Koufaty

Shahrokh Shahidzadeh

Eric L Debes

Robert P Colwell

Beeman C Strong

Ofer Levy

Raymond Scott Tetrick

Herbert H J Hum

Sham M Datta

Camron B Rust

Peter Lachner

Hermann Gartler

Itamar S Kazachinsky

Tong Li

Jonathan Jay Tyler

Madhavan Parthasarathy

Milind A Karnik

Joseph E Batz

Christine E Wang

Thilo Schmitt

Md Asifur Rahman

Ilya Wagner

M D A Rahman

Rajesh S Parathasarathy

Shammanna M Datta

Vesselin Naydenov

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

Minimizing bandwith to compress output stream in instruction tracing systems

In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Providing status of a processing device with periodic synchronization point in instruction tracing system

Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.

Processor that detects when system management mode attempts to reach program code outside of protected space

A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode

Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.

Steering system management code region accesses

Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode

Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Address space emulation

Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode

Determining length of instruction with escape and addressing form bytes without evaluating opcode

Determining length of instruction with multiple byte escape code based on information from other than opcode byte

Architectures and techniques that allow legacy pin functionality to be replaced with a 'virtual wire' that may communicate information that would otherwise be communicated by a wired interface. A message may be passed between a system controller and a processor that includes a virtual wire value and a virtual wire change indicator. The virtual wire value may include a signal corresponding to one or more pins that have been eliminated from the physical interface and the virtual wire change value may include an indication of whether the virtual wire value has changed. The combination of the virtual wire value and the virtual wire change indicator may allow multiple physical pins to be replaced by message values.

Virtualization of pin functionality in a point-to-point interface

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

Method and apparatus for performing multiply-add operations on packed byte data

Growing community of inventors

Hillsboro, OR, United States of America

Frank Binns