Nordic Semiconductor Asa

Frank Berntsen

Ola Marvik

David Alexandre Engelien-Lopes

Joel David Stapleton

Lasse Olsen

Kenneth Megard

Ole Saether

Markus Bakka Hjerto

Markus Bakka HjertØ

Ole SÆTHER

Kenneth MEGÅRD

A radio communication system comprises a radio transmitter (), and a radio receiver () configured to receive radio transmissions from the transmitter. The transmitter () uses a transmitter clock signal to transmit a succession of connection-event data packets (') according to a predetermined schedule. The receiver () enters a sleep state between receiving successive connection-event data packets from the transmitter (), in which it does not receive and process radio transmissions from the transmitter. It uses a receiver clock signal to determine when a predetermined number of receiver clock cycles has elapsed after receiving one of the connection-event data packets (&#x2032;), and then enters a ready state. The predetermined number of receiver clock cycles is the number of receiver clock cycles () that elapsed between the respective receipts of two of the connection-event data packets (&#x2032;) received by the receiver () minus a correction factor ().

Radio communication system

A system for streaming data packets, comprises a source device () having a radio transceiver (), and a receiving device () having a radio transceiver (). The source device () is configured to receive or generate a stream of data packets at a stream rate and to transmit, by radio, a succession of data frames, each data frame comprising a successive set of one or more data packets () from the stream that have not previously been transmitted. The receiving device () is configured to receive a data frame and to determine whether the one or more data packets () in the data frame have been correctly or incorrectly received and to transmit by radio an acknowledgement message () indicating that one or more of the data packets () has been correctly received and/or is configured to transmit by radio an acknowledgement message indicating that one or more of the data packets has been incorrectly received. The source device () is also configured such that, if the source device () determines that a data packet () has not been correctly received by the receiving device, the source device retransmits the data packet () in a subsequent data frame along with one or more data packets () from the stream that have not previously been transmitted. The source device () is further configured such that, if the source device does not receive an acknowledgement message () within an acknowledgement period after transmitting a data frame, the source device () retransmits the one or more data packets () from the data frame in one or more subsequent data frames along with respective one or more data packets () from the stream that have not previously been transmitted.

Streamed radio communication with ARQ and selective retransmission of packets in bursts

Synchronized radio transceivers Disclosed are a method of and apparatus for controlling a first radio transceiver () and a second radio transceiver () which are connected to a common oscillator (), wherein each transceiver () is capable of communicating with one or more remote radio transceivers (). The method comprises: &#x2022;the first transceiver () sending a synchronization signal to the second transceiver (); and &#x2022;the second transceiver () using the synchronization signal to ensure that neither transceiver () transmits data while the other transceiver is in a receiving state.

Synchronised radio transceivers

An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means () clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means () detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.

Data transfer between clock domains

An integrated-circuit device () comprises a processor (), memory () for storing executable code, and memory protection logic (). The memory protection logic () is configured to: determine the state of a read protection flag for a protected region of the memory (); detect a memory read request by the processor (); determine whether the read request is for an address in the protected region of the memory (); determine whether the processor () issued the read request while executing code stored in the protected region of the memory (); and deny read requests for addresses in the protected region if the read protection flag for the protected region is set, unless at least one of one or more access conditions is met, wherein one of the access conditions is that the processor () issued the read requests while executing code stored in the protected region.

Growing community of inventors

Heimdal, Norway

Frank Berntsen