Hitachi America, Ltd.

Hitachi, Ltd.

Frank Anton Lane

Jill MacDonald Boyce

Michael Allen Plotnick

Joshua Lawrence Koslov

John G Henderson

Larry Alan Pearlstein

Carl G Scarpa

Masuo Oku

Jack S Fuhrer

Joseph Ellis Augenbraun

Hiroo Okamoto

Takaharu Noguchi

Masafumi Nakamura

Katsuo Mohri

Sharif Mohammad Sazzad

Jack Selig Fuhrer

Joseph E Augenbruan

Koslov Joshua Lawrence

Methods and apparatus for implementing digital resampling circuits which create one or more bitstreams which include samples at desired rates, from an input bitstream having a fixed sample rate, are described. The resampling circuits of the present invention achieve the desired sample rates by performing digital interpolation on samples included in the input signal. The interpolation is performed using a filter, e.g., an all-pass infinite impulse response filter which produces an output as a function of a controllable signal delay.

Methods and apparatus for implementing digital resampling circuits

Edge detection methods and apparatus which utilize the dc dct differential data included in encoded images, e.g., an MPEG-2 encoded video stream, are described. Use of the dc dct differential data allows efficient methods for detecting the presence of edges within encoded images. The edge detection methods and apparatus of the present invention can be used where differential coding of the DC DCT coefficients is employed. Accordingly, the edge detection methods of the present invention are applicable to MPEG-2 encoded images as well as other differentially encoded images.

Methods and apparatus for detecting edges within encoded images

Methods and apparatus for simulating, in reduced resolution video decoders, the biasing effect associated with MPEG's specified rounding of pixel values including a fractional component of 0.5 to the next highest integer value are described. In one embodiment, the biasing effect is simulated by generating luminance and chrominance DC DCT coefficient bias values from, e.g., motion vector offset data. The DC DCT bias values are then added to the DC DCT coefficients of the luminance and chrominance blocks, respectively, which correspond to the same image block to which the motion vector data used to generate the bias values corresponds. In another embodiment, pixel values are directly adjusted to simulate the biasing effect associated with MPEG compliant rounding. In such an embodiment, luminance and chrominance pixel biasing values are generated as a function of, e.g., motion vector offset information. The bias values are added to the pixel values generated through the use of motion compensated prediction. The pixel values are then rounded by performing a non-biased rounding operation to generate integer pixel values.

Methods and apparatus for reducing drift due to averaging in reduced resolution video decoders

An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data. To reduce frame memory requirements inset picture data is downsampled, stored and then upsampled prior to display thereby reducing inset picture frame memory buffer requirements.

Method and apparatus for processing previously encoded video data

Digital video tape recorder ('VTR') and servo circuit for supporting the display of images during trick play VTR operation. The digital VTR, in one embodiment, having a single pair of heads of alternating azimuths located on a head cylinder one track width apart. The digital VTR records data that can be used to generate images during trick play tape speeds and directions of operation in fast scan tracks defined by the paths the single pair of heads trace over the tape during trick play operation. Each fast scan track crosses multiple normal play tracks. Sync blocks and track identification information are recorded on the tape along with video data. To align the heads with the appropriate fast scan track during trick play operation, a lookup table containing information on the pattern of fast scan tracks recorded on the tape is used. The information stored in the look-up table is compared to sync block number and track number information recorded on the tape to determine haw much the position of the tape must be adjusted to align the heads with the prerecorded fast scan tracks on the tape for the any selected speed and direction of digital video tape recorder operation.

Methods and apparatus for recording digital data including sync block

Methods and apparatus for converting a relatively low frequency signal, e.g., a 1.5 MHz signal, to a high frequency signal, e.g., a 30-100 MHz signal, in the digital domain without the need for a digital mixer operating at the high frequency are described. The high frequency represents, e.g., the ultimate digital to analog conversion frequency. In accordance with the present invention an interpolation technique is used to convert the low rate digital signal to a high rate signal and to shift the carrier to a desired frequency. This is accomplished, by first positioning the information signal, e.g., the digital waveform to be modulated on a carrier at a relatively low rate using a digital mixer operating at a fraction of the ultimate digital to analog conversion frequency. The relatively low rate signal generated by the mixing operation is then converted to a high rate signal by one or more interpolator stages. An adjustable passband filter circuit is included in each interpolation stage. In one embodiment, the adjustable passband filter circuits are implemented using a fixed frequency filter preceded and followed by frequency shifting circuits which are used to upshift and then downshift the signal being filtered. By controlling the frequency shifting adjustable filter circuits are achieved via the use of fixed filters.

Methods of performing interpolation using frequency shifting operations

Methods and apparatus for insuring that a trick play data stream, e.g., a stream of data used for fast forward or reverse playback operation, complies with preselected data standards and in particular the MPEG-2 standard are disclosed. Various methods are described for generating PCR, PTS and DTS values for a trick play data stream, which is generated from a normal play data steam, and is intended for recording in trick play segments of a tape. The described methods include generating new PCR, PTS and DTS values as a function of the trick play speed at which the data is intended to be read back. Methods and apparatus for correcting PCR, PTS and DTS values read from a tape during trick playback operation are also disclosed. The disclosed methods are directed to generating new PCRs, PTSs and DTSs to provide am MPEG-2 compliant bitstream. The described methods and apparatus are applicable to a plurality of storage and playback devices capable of implementing trick play including compact disks.

Methods for modifying a video data stream by adding headers to

Method and apparatus for extracting intra-coded video frames from a video data stream including inter-coded video frames and intra-coded video frames to produce reduced resolution intra-coded video frames suitable for recording in trick play tape segments of a tape for later play back and display during video tape recorder trick play operation. A plurality of methods and apparatus for buffering and selecting received intra-coded video frames for recording in trick play tape segments to support a plurality of trick play modes of operation are disclosed. In addition, a plurality of different data reduction methods and apparatus are disclosed for generating reduced resolution intra-coded frames from the received full resolution intra-coded video frames.

Method and apparatus for achieving video data reduction through the use

In accordance with the present invention an interpolation technique is used to convert a low rate digital signal to a high rate signal and to shift the carrier to a desired frequency. This is accomplished, by first positioning the information signal, e.g., the digital waveform to be modulated on a carrier at a relatively low rate using a digital mixer operating at a fraction of the ultimate digital to analog conversion frequency. The relatively low rate signal generated by the mixing operation is then converted to a high rate signal by one or more interpolator stages. An adjustable passband filter circuit is included in each interpolation stage. One feature of the present invention is directed to a control circuit which is response to an H bit frequency control word representing a desired output carrier frequency. The control circuit generates individual filter control signals for each adjustable filter circuit from the single H bit frequency control word. An oscillator control circuit which is responsive to a portion of the H bit frequency control word is also described.

Methods and apparatus for implementing a digital modulator

Methods and apparatus for converting a relatively low frequency signal, e.g., a 1.5 MHz signal, to a high frequency signal, e.g., a 30-100 MHz signal, in the digital domain without the need for a digital mixer operating at the high frequency are described. The high frequency represents, e.g., the ultimate digital to analog conversion frequency. In accordance with the present invention an interpolation technique is used to convert the low rate digital signal to a high rate signal and to shift the carrier to a desired frequency. This is accomplished, by first positioning the information signal, e.g., the digital waveform to be modulated on a carrier at a relatively low rate using a digital mixer operating at a fraction of the ultimate digital to analog conversion frequency. The relatively low rate signal generated by the mixing operation is then converted to a high rate signal by one or more interpolator stages. An adjustable passband filter circuit is included in each interpolation stage. In one embodiment, the adjustable passband filter circuits are implemented using a fixed frequency filter preceded and followed by frequency shifting circuits which are used to upshift and then downshift the signal being filtered. By controlling the frequency shifting adjustable filter circuits are achieved via the use of fixed filters. One feature of the present invention is directed to a control circuit which is response to an H bit frequency control word representing a desired output carrier frequency.

Methods and apparatus for implementing and controlling a digital

Methods and apparatus for re-using decoder circuitry

Methods and apparatus for performing packet synchronization recovery and error detection operation on packets including a CRC check byte, e.g., MCNS packets, are described. The present invention uses a memory during a sync acquisition mode of operation to serve as a storage device for the output of a first function circuit. The delayed bits are used as the input along with current bits from the packet stream to a second function circuit. The second function circuit generates a syndrome byte of interest. When the received packets are error free and the decoder is properly aligned with the packet structure of the bitstream, the syndrome byte of interest will assume a preselected value, e.g., 47 Hex. Once packet synchronization has been achieved, the relatively few bits output by the first function circuit which are required as delayed inputs to the second function circuit are identified and stored using a delay register which is much smaller than the memory. By switching to the delay register, the memory previously used for feedback purposes is rendered available for use during sync lock mode for other purposes. Thus, the memory can be re-used as a packet data delay memory during sync lock mode operation. In such an embodiment, received packet data is delayed one packet time period so that the generated syndrome byte corresponding to the delayed packet data can be inserted into the packet stream as the first byte of a transport data packet thereby providing an error indicator signal at the start of a packet.

Methods and apparatus for the efficient implementation of signal

Improved carrier recovery methods and apparatus suitable for use with QAM, QPSK and a wide variety of other modulation formats is described. In accordance with the invention, the phase error between received symbols, representing a frequency error, is determined using one of a plurality of techniques. The estimated frequency error is used to adjust the phase and/or frequency of a received carrier signal to achieve a frequency lock. The methods and apparatus of the present invention can be easily integrated into existing carrier recovery designs to supplement known frequency In accordance with a first embodiment of the present invention, the receipt of pairs of consecutive outer symbols is detected, a frequency error associated with each pair of consecutive symbols is generated, and the frequency error is compared to a selected threshold value to determine if it is a non-ambiguous estimate of the frequency error. If the frequency error is non-ambiguous and from a pair of consecutive outer symbols, it is used to adjust the frequency and/or phase of a received carrier signal. In the second embodiment, the receipt of pairs of consecutive outer symbols are detected. An estimate of the frequency error, determined as the phase error between received symbols, is made in the second embodiment by doing a symbol to symbol, as opposed to a symbol to target comparison.

Carrier recovery method and apparatus

Method and apparatus for controlling the position of the heads of a

Methods and apparatus for converting digital signals having a variable data rate to fixed data rate signals suitable for recording on a tape by a digital video tape recorder are disclosed. The methods include buffering of the received variable rate data, measuring the data rate of the received data for a fixed period of time and processing the buffered data to converted it into a fixed rate data stream. This processes is repeated for each of the fixed periods of time. Methods for increasing the recording time of a digital video tape recorder ('VTR') and for supporting multiple normal play modes of digital VTR operation, e.g., recording modes for recording SDTV and HDTV are also disclosed. To generate fixed data rate signals from variable data rate signals one or more of data padding and/or data reduction techniques are used. The same data reduction techniques used to generate the fixed rate data stream are used, in accordance with various embodiment of the invention, to reduce the amount of data required to represent a video frame.

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Medford Lakes, NJ, United States of America

Frank Anton Lane