Micron Technology Incorporated

Mcron Technology, Inc.

Frank Alejano

Timothy B Cowles

Tyler J Gomm

Howard Kirsch

Danial S Dean

Brian J Ladner

Paul M Prew

Todd A Merritt

Todd A Merrit

A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.

Zero-enabled fuse-set

A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an in put clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and failing edges of the input clock signal.

Delay-locked loop circuit and method using a ring oscillator and counter-based delay

A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an input clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and falling edges of the input clock signal.

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Allen, TX, United States of America

Frank Alejano