Infineon Technologies Ag

Frank Adler

Martin Versen

Thomas Huber

Manfred Moser

Hartmut Berger

A test device for dynamic memory modules is described and has an electronic test unit for generating test signals. Accordingly, the electronic test unit has at least one electronic component for generating the test signals, and is configured for use on a personal computer mother board and contains at least one memory controller.

Test device for dynamic memory modules

A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.

Method for the defect analysis of memory modules

Two methods check functional capability of electrical connections between address lines of a printed circuit board of a memory module and address line contacts of an integrated semiconductor memory chip mounted on the printed circuit board. Ruptured solder contacts are conventionally examined optically or investigated by electrical resistance measurements; however, the latter do not work in the case of memory modules with a number of semiconductor chips, the pin contacts of which are connected in parallel by the address lines. The methods make it possible to locate interrupted contacts on individual address lines by the indirect use of a write-read access to the semiconductor memory chip, specifically utilizing the misrouting of writing and reading commands produced by defective contact connections.

Method of checking electrical connections between a memory module and a semiconductor memory chip

A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.

Circuit for testing an integrated circuit

Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using automatic standard test equipment composed of a standard test unit and a performance board with fittings attached thereto. In that first, using a standard routine of the test unit, a transit time is measured on the performance board from the CIF connector as far as the fitting, then a printed circuit board is plugged into the fitting location determined for it and then the sum transit time of the CIF connector is measured as far as the landing pad on the printed circuit board. By forming differences between the two measured values, the transit times on a printed circuit board can be measured with a high degree of precision with the automatic standard test equipment used in standard module testing technology.

Method for determining the transit time of electrical signals on printed circuit boards using automatic standard test equipment

A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for supplying and extracting the etchant. The device contains two cylindrical lines of different cross-sectional areas, of which the cylindrical line with the smaller cross-sectional area is guided inside the cylindrical line with the larger cross-sectional area. An etchant is fed through the inner line to the region of the semiconductor wafer that is to be etched, and the etchant that spreads out beyond the region of the surface that is to be etched is extracted through the outer line. The cross-sectional area of the outer line is less than or equal to the area of the region of the surface which is to be etched.

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Munich, Germany

Frank Adler