Tandem Computers Incorporated

Burroughs, Inc.

Compaq Computer Corporation, Inc.

Frank A Williams

David P Sonnier

Daniel L Fowler

David J Garcia

William P Bunton

William J Watson

William Edward Baker

Robert W Horst

Geoffrey I Iswandhi

Paul N Hintikka

Mark R Scheevel

John D Coddington

William F Bruckert

Richard W Cutts, Jr

Susan S Meredith

Gary L Logsdon

Curtis Willard Jones, Jr

Gary F Campbell

John Michael Brown

John C Krause

Douglas E Jewett

Steven C Meyers

Stephen G Low

Patricia L Whiteside

Linda Ellen Zalzala

Randall G Banton

James Stevens Klecka

Stephen H Miller

Barry Lee Drexler

Harry Frank Elrod

Self-checked, lock step processor pairs

A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages therebetween. The messages contain address information identifying the source and destination of the message, and may also contain requests to write to, or read from, storage of a CPU. Protection against errant reads or writes is provided by an access validation method that utilizes access validation information contained in plural entries maintained by each CPU. Each entry provides validation by identifying what elements of the system has read and/or write wccss to the memory of that CPU, without which memory access is denied.

Storage access validation to data messages using partial storage address

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Fail-fast, fail-functional, fault-tolerant multiprocessor system

The present invention provides a mechanism for initial execution of software code by a processor in a multiprocessor system. In the preferred embodiment, the multiprocessor system has registers implemented at a reset vector location in a processor. The registers are first loaded with a sequence of software code, and then a first instruction loop is implemented with that software code. The processor is then released from a reset state, and the first instruction loop is executed. This first instruction loop is capable of being executed for an indefinite length of time, and it can execute software instructions on a periodic basis. The first instruction loop is then modified into a second instruction loop. The first and second instruction loops have at least one different instruction. The processor within the system of multiple processors is thus initialized.

Spoon-feed initialization in a multiprocessor system

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.

Interrupt message delivery identified by storage location of received

A parallel register-transfer mechanism and control section have been disclosed above for use in a reduction process for the evaluation of expressions of a variable-free applicative language stored as binary directed graphs. The expressions are reduced through a series of transformations until a result is obtained.

Graph manager for a reduction processor evaluating programs stored as

An allocator for a reduction processor which evaluates programs stored as binary graphs employing variable-free applicative language codes. These graphs are made up of nodes, each of which exists in memory and contains as its most significant bit a mark bit which when set indicates that the node is being used in a graph and when reset indicates that the node or storage location is available for future use by the processor. The allocator scans selected groups of storage locations in parallel to see if there are any unused storage locations and then places the addresses of those unused storage locations in a queue for use by the processor.

Allocator for a reduction processor evaluating programs stored as binary

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Austin, TX, United States of America

Frank A Williams