3com Corporation

Digital Equipment Corporation

Frank A Itkowsky

Cary B Robins

James Scott Hiscock

Kadangode K Ramakrishnan

G Paul Koning

John Ernest Ziegler

Brian Ramelson

Gary D Lorenz

Stanley Chmielecki

Ching S Lee

Andreas Bovopoulos

Peter Driscoll

Douglas M Washbaugh

Shirish B Dandekar

Symmetric flow control in a buffered repeater having responsiveness to flow control frames. An Ethernet full duplex buffered repeater according to the present invention includes an internal arbitration mechanism allowing receive FIFOs of respective receive ports to transmit data over a local bus to remaining transmit ports in round-robin fashion. The transmit ports take the transmitted data off the local bus and transmit it over the respective link. Each transmit port monitors the capacity of an associated transmit FIFO, and when the available capacity falls below that required to store a maximum size frame, asserts an open collector output signal monitored by each of the ports. No port initiates transmission of a packet over the local bus when this signal is asserted. Rather than one of the transmit ports risking being unable to store a complete frame once transmission has begun, the local bus is suspended before the next frame is put on the local bus. As the receive FIFOs fill, Pause Frames are issued by the respective port over each associated link. Each port is responsive to received flow control frames for pausing transmission of data over the respective link. Each buffered repeater is cascadable with other such devices to implement an arbitrarily large buffered repeater.

Symmetric flow control for ethernet full duplex buffered repeater

A computer network system containing a concentrator with a backplane that has a plurality of lines. The backplane contains data lines and control lines for managing and organizing the transfer of data between modules in the concentrator. The system contains an intelligent bus arbiter system that allow the selection of transmitting modules to occur at the same time as actual data transfer is going on between other modules. The bus arbitration system is provided for determining a sequence of bus access. A memory is provided for building a table comprising entries. Each of the entries represents a module slot identification number. Each entry also has an entry link portion which links a given entry to another entry. The system also includes arbiter logic cycling through or sequencing through and reading the table from one entry to another entry based on the entry link portion. The arbiter logic forms an output of a current slot identification number, corresponding to the module which is to have access to the bus. With this system, the number of entries having a particular module slot identification number relative to the total number of entries in the table determines a proportion of access to the bus of the module having the particular module slot identification number thereby allowing updating to the table to change access to the bus more readily.

Arbitration system using linked table

A computer network system containing a concentrator with a backplane that has a plurality of lines. The backplane contains data lines and control lines for managing and organizing the transfer of data between modules in the concentrator. The system contains intelligent devices that allow the selection of transmitting modules to occur at the same time as actual data transfer is going on between other modules. This is preferably done in a round robin arbitration process where, while data is being transferred by a first module, a bus arbitration device is placing addresses of modules which sequentially follow the transmitting module onto the control lines. Modules will see their address on the control lines, and if they have a packet to transmit, they then reserve the right to transmit after the presently transmitting module is finished. In this way the selection of the next module to transmit is performed in parallel, and does not slow down, the transfer of data between modules. The control lines are also able to indicate when a receiving module has been unable to copy a packet. The transmitting module can then resend the packet for either a maximum number of retries, or until the receiving module is able to copy the packet.

High speed communication bus

An apparatus and method for transferring data in a data processing system to and from a host system. A communication adapter or input/output controller device is provided in which queues are utilized to transfer information between the adapter or controller and the host system. In order to minimize the amount of time a system or I/O bus or network is used during transfer of data between the adapter or controller and the host system, and reduce the amount of work that must be performed by the host system, the number of interrupts by the adapter or controller of the host system is limited to the minimum amount necessary by using an interrupt arm mechanism and by keeping track of completion indices stored in the host system.

Apparatus and method for controlling interrupts to a host during data

An apparatus and method for transferring data via DMA in data processing system from a host system to a transmission network. The transferred data is in longword format in which each longword consists of four bytes. Within a longword, valid bytes intended for transmission are contiguous. The adapter or I/O device includes a packet memory and a FIFO circuit interposed between the host system and packet memory to allow for differences in access speed of a host memory and the packet memory. The FIFO circuit contains four discrete FIFO circuits that are separately addressable for writing the bytes of each longword received from the host memory for storage in the FIFO circuit. The received longword is applied to a barrel shifter which aligns the first valid byte in the received longword with the one of the four discrete FIFO circuits containing a first available storage location at a current FIFO longword address. A FIFO control circuit receives information describing the number of valid bytes in the received longword and generates a control signal to control the barrel shifter and FIFO address signals to cause the valid bytes of the received longword to be stored in contiguous byte positions in the FIFO circuit commencing with the first available storage location.

Apparatus and method for aligning data transferred via DMA using a

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Leominster, MA, United States of America

Frank A Itkowsky