Sgs-thomson Microelectronics S.a.

Sgs-thomson Microelectronics Limited

Stmicroelectronics S.a.

Francois Tailliet

Jacek A Kowalski

Richard P Fournel

Jean-Marie Bernard Gaultier

Serge Fruhauf

To protect integrated circuits as efficiently as possible against electrostatic discharges, by putting a diode in avalanche mode without untimely triggering of this avalance mode by overvoltages of non-electrostatic origin, the following solution is proposed: through an insulated gate surrounding the cathode of the diode, the threshold for transition into avalanche mode of the diode is modified according to the slope of the overvoltages appearing at the terminal to be protected. The gate is connected to the terminal by an integrating circuit in such a way that the overvoltages are applied to the gate with a certain delay, inducing a potential difference between the cathode and the gate which is all the greater as the front of the overvoltage is steep. The avalanche triggering threshold is higher in the latter case than in the former one, and it is thus distinguish between overvoltages of diverse origins.

Integrated circuit protected against electrostatic discharges, with variable protection threshold

A device for the programming of cells of an electrically programmable non-volatile memory. The device comprising a first reference input for receiving an erase signal for erasing one or more memory cells in the non-volatile memory and a second reference input for receiving an programming signal for programming one or more memory cells in the non-volatile memory. A regulation circuit coupled to the first reference input and coupled to the second reference input for regulating the magnitude of an erasure signal and for regulating the magnitude of a programming signal so that an electric field of approximate equal absolute magnitude is created on the floating gate of one or more memory cells during an erase type operation and an programming type operation.

Method and device for the programming of an electrically programmable non-volatile memory for improved reliability

To increase the integration density of an EEPROM type memory, it is chosen to do without the selection transistor. To then arrive at a selection operation in erasure, programming or reading modes, it is chosen to apply negative voltages or voltages with a value half that of a programming voltage (VPP) to certain connections (with r' different from r) of the memory.

Non-volatile electronic memory and method for the management thereof

In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantageously used to protect MOS type integrated circuits against electrical discharges.

Method for making a bipolar transistor for the protection of an

In an integrated circuit, a diode is interposed between the semiconductor substrate and the contact pad to an external bias voltage, and the substrate is biased at an internal voltage reference. Between each contact pad of the integrated circuit and semiconductor substrate, there is positioned a protection device against permanent overloads and a protection device against electrostatic discharges. By isolating the semiconductor substrate from the external voltages source and by placing a protection device between each contact pad and the substrate, a broad, general protection of the integrated circuit is obtained against all the destructive phenomena such as overloads, positive and negative overvoltages, polarity reversal and electrostatic discharges.

General protection of an integrated circuit against permanent overloads

A resistor-capacitor-transistor type of integrated circuit comprises mainly a non-self-aligned N diffusion bar 1 covered with a polysilicon plate, and a drain type N diffusion, self-aligned by the polysilicon plate. The resulting structure is a distributed resistor-capacitor-transistor quadripole whose main characteristics are that it is very compact and that the time taken by the capacitor to get discharged through the transistor is independent of the dimensions of the structure.

Resistor-capacitor-transistor type integrated circuit, method for the

A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure.

Protection structure against latch-up in a CMOS circuit

A circuit for the detection of a fuse with oxide vertical fusing has another fuse that is of the same type but cannot be blown and, in parallel with each of the fuses, a voltage reference circuit. The output of each of the voltage reference circuits is an input of a differential comparator. This differential comparator is preferably provided with a voltage reference circuit that is independent of the supply voltage Vcc.

Circuit for detection of the state of an integrated circuit fuse in a

The disclosure concerns integrated circuits and, more particularly, their protection against electrostatic discharges. To protect a metallized pad in a CMOS circuit on an N substrate with P wells, an NPN type lateral bipolar transistor formed in a P-type well is used. The emitter is an N+ region connected to the pad. The collector is an N+ region connected to a metallization which is itself connected, like the substrate N, to the high supply voltage Vcc of the circuit. The well is taken to the potential of the pad to be protected by means of an ohmic contact by a P+ surface diffusion of the well. In the preferred embodiment of the invention, the region that acts as a collector includes a part extending laterally outside the P well, and it is in this external part that the contact with the metallization occurs. The contact is at a sufficient distance from the well for there to be no risk of damage to the trench/substrate junction when the density of current flowing through the metallization is high.

CMOS integrated circuit structure protected against electrostatic

The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray thyristor is triggered by artificially making the potential drop in an intermediate region of the pad. The thyristor always comes on suddenly, the current that flows through the thyristor is very high and the phenomenon stops spontaneously when the fuse is melted.

Fuse-melting device

In the substrate (23) of an integrated circuit, around a pad area, a first region (24) of the first conductivity type having a high doping level in turn formed in a second region (25) of the second conductivity type and, beyond the first region with respect to the pad, a third region (26) of the second conductivity type at least partially in contact with the second region, are formed. The pad metallization (20) also establishes a contact with a portion (27) of the first region surface. A second metallization (30) connects the first region to the third one at such a location that the current path between, on the one hand, the contact area between the pad metallization and the first region and, on the other hand, the area where the third region forms a junction with the substrate (corresponding to an avalanche diode) follows a resistive path in at least one of the first or third regions.

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Epinay sur Seine, France

Francois Tailliet