Stmicroelectronics (Rousset) Sas

Stmicroelectronics S.a.

Stmicroelectronics International N.v.

Stmicroelectronics (Grenoble 2) Sas

François Tailliet

Marc Battista

Gilles Bas

Victorien Brecte

Hervé Chalopin

Chama Ameziane El Hassani

Guilhem Bouton

Laurent Murillo

Yvon Bahout

Roberto Simola

Francesco La Rosa

Luc Wuidart

Thierry Giovinazzi

Philippe Ganivet

Christophe Goncalves

Beatrice Brochier

Sylvain Fidelis

A nonvolatile memory device has a 'split-voltage' architecture and includes columns of memory words formed on each row by groups of memory cells. All state transistors for memory cells of a memory word are gate controlled by a control element. All control elements of a same row are controlled by a first control signal generated by a first row control circuit in response to a set-reset (SR) latch output signal output for a selected row. In order to write a piece of data in a memory word, the first row control circuit confers onto the first control signal an erasing voltage corresponding to a first logic state of the first control signal and then a programming voltage corresponding to a second logic state of the first control signal without modifying, between erasing and programming the memory word, the state of the latch output signal for the selected row.

Device of the EEPROM memory type with an architecture of the split voltage type

Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.

Aging proof delay circuit

The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

Latch device, in particular for row decoding and column decoding of an EEPROM memory plane

According to an embodiment, a buffer circuit for a communication interface is disclosed. The circuit includes a charge pump to boost a supply voltage and generate a boosted supply voltage. The circuit features a resistor, a capacitor connected to the output, and multiple transistors. This configuration ensures efficient voltage boosting and buffering for enhanced communication interface performance.

IC buffer circuit with fall time control

An ESD protection circuit includes a first voltage limiter having a first input terminal electrically coupled to each first signal pad of an integrated circuit by a first diode mounted in reverse bias during the integrated circuit operation. The first voltage limiter is mounted to be conductive between each first signal pad and ground during a positive ESD on the first signal pad. A second voltage limiter is electrically coupled and mounted to be conductive in the same direction as the first voltage limiter, between an external power supply pad and ground. An internal node outputs an internal power supply voltage to the domain, and is passed through by a current in response to a positive ESD on the power supply pad which is lower than the current passing through the first voltage limiter. A blocking diode is electrically connected between the first input terminal and the power supply pad.

Protection of an integrated circuit against electrostatic discharges

A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components according to their position in test semiconductor wafers; associating, with each component of each chip, auxiliary correction elements; activating by masking the connection of the correction elements to each component according to the initial mapping.

Low-dispersion component in an electronic chip

An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

Compact EEPROM memory cell with a gate dielectric layer having two different thicknesses

The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.

Communication on an I2C bus

An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node.

Non volatile static random access memory device and corresponding control method

A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.

Test circuit

The present description concerns an electrostatic discharge protection device including a first clipping circuit coupled between a first node and a second node and a second active clipping circuit, series-coupled with a first resistor, the second clipping circuit and the first resistor being coupled between the first and second nodes, the second clipping circuit including a field-effect transistor having a metal-oxide-semiconductor structure.

Electrostatic discharge protection device

A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

Method for writing an electrically erasable and programmable non volatile memory and corresponding integrated circuit

An integrated circuit comprises a memory device including at least one memory point having a volatile memory cell and a single non-volatile memory cell coupled together to a common node, and a single selection transistor coupled between the common node and a single bit line. A first output of the volatile memory cell is coupled to the common node, and a second output of the volatile memory cell, complementary to the first output, is not connected to any node outside the volatile memory cell.

A non-volatile memory device includes a substrate, a plurality of memory words, a control block, a first electrically-conducting link, and a plurality of second electrically-conducting links. The substrate includes a substantially planar surface. The memory words include B memory words disposed at the substantially planar surface. The control block includes B control elements disposed at the substantially planar surface. The first electrically-conducting link is disposed in a first plane parallel to the substantially planar surface. The first electrically-conducting link connects one of the B control elements to a memory word of the memory words. The plurality of second electrically-conducting links includes B-1 second electrically-conducting links respectively connecting B-1 remaining control elements to B-1 corresponding memory words of the plurality of memory words. The B-1 second electrically-conducting links are disposed above the first plane and physically extend at least partially over at least two memory words of the memory words.

Growing community of inventors

Fuveau, France

François Tailliet