Vlsi Technology, Inc.

Vsli Technology, Inc.

Francois Silve

Arnold Ginetti

Jean-Michel Fernandez

Mossaddeq Mahmood

Balmukund K Sharma

Athanasius W Spyrou

Jean-Charles Giomi

Jean-Michel Fernandes

Philippe Troin

Ginetti Arnold

Gerrard Tarroux

Satish Raj

A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.

Method and system for floorplanning a circuit design at a high level of abstraction

A set of flat net descriptors are added to a hierarchical representation of a specified circuit design so as to provide a hierarchical view and a flat net view of the circuit design. The hierarchical representation includes a set of cell descriptors representing hierarchical cells in the specified circuit design, and a set of net descriptors representing portions of interconnections located within each hierarchical cell. Each net descriptor has associated therewith a list of endpoint descriptors representing endpoints of a corresponding one of the interconnections located within a respective hierarchical cell. The procedure for generating flat nets generates a flat net descriptor for each interconnection in the specified circuit. Each flat net descriptor has associated therewith a list of endpoint descriptors representing all endpoints of the interconnection. Each of the endpoint descriptor associated with a flat net descriptor represents an interconnection endpoint in a flat, top level circuit representation of the specified circuit design. A flat net pointer is added to each net descriptor in the hierarchical representation of the specified circuit design. The flat net pointer points to an associated one of the flat net descriptors. As a result, a flat net representation of any interconnection in the specified circuit design is accessible through the flat net pointer in each of the net descriptors representing the interconnection.

Computer aided design system and method using hierarchical and flat

A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.

System to fix post-layout timing and design rules violations

A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.

Logic synthesis constraints allocation automating the concurrent

In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable. The computer aided design system then automatically verifies that the integrated circuit satisifies the specified timing constraints. During the timing constraint verification process, for mutli-clock timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated only through signal paths consistent with the constraint based timing path specifications. In addition, the verified netlist, timing constraints and constraint based timing path specifications may be passed to a silicon compiler for automatically placing/routing a circuit in accordance with the netlist, timing constraints and constraint based timing path specifications.

Method and a system for specifying and automatically analyzing multiple

A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

Method for improving the operation of a circuit through iterative

Process for the processing of logic function specification data of an associated specific integrated circuit or ASIC for a graphical representation of said circuit. The process consists of associating with the specification data Boolean attributes as a function of aspects, characteristics and details which a user wishes to know with respect to the circuit and then constructing data representative of said characteristics. One representation of the circuit can then be displayed by associating graphical symbols with the constructed data.

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le Cannet, France

Francois Silve