Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Philips Semiconductors Inc.

Francois Niot

Roland Van Der Tuijn

The present invention provides digital computers, memory interfaces, methods of executing a program, methods of programming a digital computer, and methods of operating a memory interface. According to one embodiment, the present invention provides a digital computer including a memory unit configured to store program code including a plurality of ordered program instructions; a processor electrically coupled with the memory unit, the processor being configured to request fetching of program instructions from the memory unit, the processor being further configured to decode and execute the fetched program instructions; and a memory interface electrically coupled with the memory unit and the processor, the memory interface being configured to generate a substitute instruction and fetch program instructions from the memory unit responsive to a request from the processor, the memory interface being further configured to selectively output the fetched program instructions and the substitute instruction to the processor.

Reduced instruction fetch latency in a system including a pipelined processor

A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the program instructions. The program memory stores the set of program instructions such that the microprocessor can retrieve the set of program instructions regardless of which bit-width is used to store the set of program instructions. Additional circuitry maps the address signals for retrieving the program instructions from the program memory.

Microprocessor configuration arrangement for selecting an external bus width

A radio controller arrangement for controlling communication signal timing in a duplex radio-frequency TDMA radio includes a TDMA timer that generates a receive timing signal and a microprocessor circuit. The microprocessor circuit commands the TDMA timer to activate the radio to receive a signal and converts the signal into packets having synchronization and data fields. The TDMA timer synchronizes a beginning of a data collection operation to the synchronization field and locates the beginning of the data field based on the end of the synchronization field. The TDMA timer collects data from the data field until it detects the end of the data field. The TDMA timer then commands deactivation of the radio. The radio controller arrangement may be incorporated into a communication device or used in connection with a method for controlling communication signal timing.

Communication timing control arrangement and method thereof

An arrangement for providing key switch actuation detection which reduces the number of key switch inputs required at a key switch controller. A key scanning system for detecting the activation of keys on a key-based input device is provided, having a plurality of logic level sensors to detect and temporarily store logic levels on corresponding connection nodes. A plurality of switches, each coupled to one of the keys, provides a pattern of logic levels on the connection nodes in response to the activation of a particular key. A logic monitor is coupled to the logic level sensors to detect the stored logic levels and recognize the activation of the particular key based on the pattern of the stored logic levels. A method for performing key switch actuation detection that reduces the number of required key switch inputs is also provided.

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Biot, France

Francois Niot