Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.a.

Francois Leverd

Philippe Coronel

Pierre Bar

Delia Ristoiu

Thomas Skotnicki

Francois Roy

Michel Marty

Joaquin Torres

Paul Ferreira

Jens Prima

The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Etching method

A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

Method of etching a cavity in a stack of layers

An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.

Process for fabricating a backside-illuminated imaging device and corresponding device

A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints. In a preferred method, a selective treatment is applied to the transferred part of the initial structure, so as to make a distinction between the volumes of differentiated material of the pattern.

Electronic components and method of fabricating the same

An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Isolating trench and manufacturing process

The invention relates to a process for protection of the grid of a transistor in an integrated circuit for production of a local interconnection pad straddling over the grid and the silicon substrate on which it is formed. The process consists of applying a double dielectric-conducting layer on the transistor grid into which a polysilicon layer is added in order to use the selectivity principle, which is large considering the etching of polysilicon with respect to the oxide in which the local interconnection pad is formed. Furthermore, with the process according to the invention, a silicidation treatment can be applied beforehand on the active areas of the transistor and the grid.

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Saint Ismier, France

Francois Leverd