International Business Machines Corporation

Francois Le Maut

Rene J Glaise

Michel Poret

Alain R Blanc

Rene Gallezot

Daniel Wind

Jean-Claude Abbiate

Bernard Brezzo

In a network device packets are marked with sequence identifiers at ingress of the device, switched through a plurality of switching planes and re-sequenced on a per flow basis at egress of the device. The re-sequencing system includes a controller that allocates to each received data packet a temporary storage location in a packet buffer. A plurality of output registers are provided, with each one associated with a flow. A pointer uses predefined parameters to point to an output register that has been previously assigned to receive data packets from the corresponding flow. Parameters in the pointed output register are correlated with parameters in a received packet to determine if the received packet is next in sequence to packets processed through a particular queue.

System and method for re-sequencing data packets on a per-flow basis

A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.

Algorithm and system for selecting acknowledgments from an array of collapsed VOQ's

A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.

Event-driven flow control for a very high-speed switching node

A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets 'WPC' temporarily stored within an egress buffer to a predefined threshold value 'WPCth'. The packet sequence number &#x2018;PSNr&#x2019; of a last received in-sequence data packet and each highest packet sequence number &#x2018;HPSNj&#x2019; received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number &#x2018;PSNr&#x2019; to each highest packet sequence number &#x2018;HPSNj&#x2019; when the number of data packets &#x2018;WPC&#x2019; exceeds the predefined threshold value &#x2018;WPCth&#x2019; a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Packet unstopper system for a parallel packet switch

A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Data packet switch and method of operating same

A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion. Furthermore, since a packet is admitted in the switch core only if it can be transmitted to the corresponding egress buffer, the shared memory is reduced.

System and method for collapsing VOQ's of a packet switch fabric

A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time. Analyzing all the ingress ports holding at least one data packet, from the lesser degree of freedom to the greater degree of freedom, the algorithm determines as many virtual output queues as possible, in the limit of the number of ingress ports (an ingress port may send only one packet per packet-cycle).

A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g., for replacing the defective individual switching plane or device.

Method and system to enable an adaptive load balancing in a parallel packet switch

A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm. The queue scheduling mechanism further includes an exhaustive priority register that registers the value of at least one exhaustive priority rank to be read by the queue scheduler from the queue device corresponding to the exhaustive priority rank rather than from the queue device corresponding to the priority N.

Queue scheduling mechanism in a data packet transmission system

The invention permits an effective traffic flow control, down to all sub-ports, of a switch made of a N-port core switch fabric. Sub-ports concentrate traffic from lower speed lines to a switch fabric native port. In each sub-port adapter, when congestion is detected in the OUT leg, it is reported through the corresponding IN leg. Congestion is piggybacked over the incoming traffic entering the input port of the N-port core switching fabric and is broadcast so that all sub-ports become aware of the detected congestion in any of the sub-ports. Each sub-port adapter performs a checking of the congestion status of all the other sub-ports and acts to stop forwarding received traffic destined for congested sub-ports and holds further received traffic until the sub-ports are reported to be no longer congested. The full intrinsic performance of a N-port switch fabric is realized by concentrating, through port and sub-port adapters, the traffic of more than N independent lines.

System and method for enabling a full flow control down to the sub-ports of a switch fabric

The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.

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Nice, France

Francois Le Maut