International Business Machines Corporation

Cisco Systems Inc.

Rpx Clearinghouse LLC

Francois Kermarec

Rene J Glaise

Aline Fichou

Bernard Y Pucci

Maurice Duault

Claude Basso

Claude R Galand

Jean L Calvignac

Marc Lamberton

Gerard Richter

Hans Rudolf Schindler

Laurent Nicolas

Andre Pauporte

Pierre-Andre Foriel

Michael Tate

Eric Lallemand

Eric Mouque

Haissam Alaiwan

Tan T Pham

Regis Carpentier

Thanh Pham

Serge Leroy

Jacques-Louis Combes

A virtual private network (VPN) service is provided through a shared network infrastructure comprising interconnected provider edge (PE) devices having customer edge (CE) interfaces. Some of the CE interfaces are allocated to a VPN supporting virtual LANs. A correspondence between a CE interface and a virtual LAN is learnt on the basis of tagged frames received at this CE interface and including an identifier of this virtual LAN. The learning process permits the detection of pairs of CE interfaces which correspond to a common virtual LAN. Upon such detection, a virtual circuit is established in the shared network infrastructure between the PE devices having these CE interfaces, and subsequently used for forwarding frames including the identifier of the common virtual VLAN.

Methods of establishing virtual circuits and of providing a virtual private network service through a shared network, and provider edge device for such network

An adaptive apparatus and method for managing a playout buffer (POB) in an edge node of a packet-based data communications network, such as an ATM network, in order to reduce the end-to-end communication delay introduced thereby and to allow the POB filling level to be corrected in the event of clock speed differences. A monitoring mechanism determines if the minimum filling level of the playout buffer over a time period whereby the average filling level of the playout buffer is reduced according to the minimum filling level of the playout buffer over the time period.

Adaptive playout buffer and method for improved data communication

The swapping function of input values to output values is performed through a pseudo content addressable memory which provides output values corresponding to a number E of n-bit input values, with E&equals;2 &minus;1. The pseudo content addressable memory is made of a plurality of cascaded random address memories having at least a 2 addressing capability, with d higher than p. A control logic circuit is provided to store into each random access memory p-bits pointers, with each pointer being different from the others and randomly assigned to an input value. In order to find an output value corresponding to an input value, the control logic circuit sequentially address and reads the cascaded random access memories, the first memory being addressed with a part including a number n1 of bits of the input value, and each one of the next memories being addressed with the pointer read from the preceding memory concatenated with another part ni of bits of the input value, with ni equal to or lower than n&minus;n1. The output value is found as a result of the addressing of the last memory.

Apparatus for swapping input values into corresponding output values

In high speed cell switching networks, a Call Admission Control (CAC) procedure is performed on each connection according to a specified Traffic Descriptor. A mandatory parameter of the Traffic Descriptor is the Peak Cell Rate (PCR), associated with a Cell Delay Variation Tolerance (CDVT). Connections which specify a high CDVT value may potentially send into the network bursts of cells at a rate much higher than the declared Peak Cell Rate, which may lead to congestion in cell buffers of intermediate network nodes. Guaranteeing the Quality of Service (QoS) for such connections may require the reservation of a high amount of resources in the network, leading to poor utilization of those resources. A Call Admission Control procedure, associated with an Usage Parameter Control/Network Parameter Control mechanism, provides:

Flow control for very bursty connections in high speed cell switching

A method and an apparatus for reducing the jitter and end-to-end delay on lines of a packet switching network conveying voice or video digitalized data for one or more connections between a local source and a remote source at a constant bit rate. The method and apparatus of the invention are for use in a voice or video processor of a voice or video processing server of a network node; the method and the apparatus provide a way of controlling the remote traffic rate from the remote source before accessing the processor without using an external clocking such as the network clock. The solution proposed by the invention consists in buffering the remote and local traffics to adapt the remote traffic rate to the local traffic rate, which is supposed having a limited jitter, while sequencing of the access of the buffered data to the processor.

Method and apparatus to reduce jitter and end-to-end delay for

A method and an apparatus for shaping the output traffic in the transmit part of a network node adapter. The network node supports fixed length cell switching user information traffic between a source unit and a destination unit. The method and apparatus use two lookup tables called an active and a standby calendar per output line. Each entry in the calendars represents the position of one cell in the output cell stream. Three parameters tables are used to store the information on user traffic in the descending order of the user bandwidth share negotiated at traffic establishment time for the calendars. The active calendar is continuously read by a transmit device and the corresponding cells are sent onto the output line. Under control of a control device, a placement device places entries in the standby calendar reserved as changes occur in the traffic. Once filled up, the standby calendar is swapped to the active calendar and is read by the transmit device.

Method and an apparatus for shaping the output traffic in a fixed length

A device which switches data processing from an active processor, about to fail, to a back-up processor includes a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establishing recovery point signals generated by the active processor to be dumped into the memory of the back-up processor so that the back-up processor resumes operation of the active processor from the last established recovery point.

Checkpointing mechanism for fault-tolerant systems

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Cagnes-sur-Mer, France

Francois Kermarec