International Business Machines Corporation

Francois Jacob

Andre Pauporte

Clement Y Poiraud

Michel Geneste

A fan system to be mounted over an opening including a plurality of pivoting blades fixed on a free wheeling element and a motor driven element wherein, in operation, when the fan is operating the motor driven element pivots the blades to a blowing position allowing air flow through the opening, and when the fan is not operating a resilient member pivots the blades to a closed position preventing air flow through the opening.

Fan with self closing blades

The object of the present invention is to improve the execution of instructions using speculative operations in Superscalar or Very Long Instruction Word (VLIW) processors having multiple Arithmetic Logic Units (ALUs). More particularly, the invention relates to a system and method for using standard registers as shadow registers. The addresses of all standard registers are translated using a Relocation Table (RT) array. The addresses of registers used as shadow registers are translated another time using a Speculative Registers Table (SRT) array. At branch completion time, for the speculative operations that have previously been executed and correctly predicted, the Relocation Table (RT) is updated with the Speculative Registers Table (SRT) content. For the speculative operations that have previously been executed and incorrectly predicted, the Relocation Table (RT) remains unchanged. The present invention performs the same function as processors using state of the art hardware shadow registers while using a limited number of read/write ports standard register array.

Speculative instructions exection in VLIW processors

Processing system for interpreting and carrying out a set of logically related instructions stored into a software program, the execution of a given instruction by the processing system involving the decoding and the execution of a corresponding set of microcommands. The processing system stores a signature portion corresponding to the macrocommand portion of a given instruction which is to be interpreted and executed, and signature data in response to the actual decoding and execution process of the microcommands involved in the execution of the instruction. The processing system further compares the computed signature data with the signature portion in order to detect the occurrence of an error in the decoding and execution process of the given instruction. In one embodiment of the invention, the processing system is such that one instruction is interpreted and executed in one elementary machine cycle. In a second embodiment of the invention, the execution of a given instruction involves the succession of multiple elementary machine cycles.

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Vence, France

Francois Jacob