Lsi Logic Corporation

Francois Ducaroir

Michael O Jenkins

Karl S Nakamura

Rong Pan

Krishnan Ramamurthy

Brett D Hardy

Marc A Miller

Christian Joly

Zarir B Sarkari

Allen Wu

Michael Okronglis

Ross MacTaggart

A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

Serial data transmitter with bit doubling

A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter. As a result, the received serial data is retransmitted by the transceiver. A test method involves asserting the test signal, providing serial input test data to a serial data input port, receiving serial output test data from a serial data output port, and comparing the serial output test data to the serial input test data. A match between the serial output test data and the serial input test data verifies proper operation of the serial data transceiver.

Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method

A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. A receiver of the transceiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port. The receiver includes a deserializer which receives the serial data stream, recovers the transmit clock signal used to transmit the serial data from the serial data stream, generates a timing signal based upon the recovered transmit clock signal, samples the serial data stream using the timing signal in order to recover the data from the serial data stream, aligns the deserialized data into parallel units, and provides the resulting parallel data at the receive data output port. The deserializer samples the serial data stream within each data window dependent upon the duty cycle of the timing signal. The deserializer varies the duty cycle of the timing signal according to a received control signal in order to facilitate measurement of the amount of jitter within the serial data stream.

Serial data transceiver architecture and test method for measuring the amount of jitter within a serial data stream

One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent. Each transmit unit comprises a receiver operably coupled between an input port and an output port, and a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. Also included are a transmitter which receives parallel data and transmits a serial data stream. The parallel data are received concurrently with the serialized data being received. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream.

High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network

An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies. The multiplexer provides the reference clock signal to the first transceiver when the test signal is deasserted, and provides the test clock signal to the first transceiver when the test signal is asserted. During testing, the output of the transmitter of one transceiver is coupled to the input of the receiver of the other transceiver, and the test signal is asserted. Each receiver produces parallel output test data. A match between the two sets of parallel output test data and the parallel input test data demonstrates the abilities of both transceivers to transmit and receive serial data at different frequencies.

Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency

A transceiver pair is connected by a plurality of high speed serial lines that are tightly integrated into an enhanced communications system. The communications system includes a base transceiver, a remote transceiver, and a plurality of high speed serial lines operably coupled between them. The base transceiver includes a first base input port for receiving parallel data, a plurality of first base output ports for outputting serialized data and a plurality of base serializers operably coupled between the first base input port and the plurality of first base output ports. The plurality of base serializers convert the parallel data into the serialized data. A base input demultiplexer is operably coupled between the first base input port and the plurality of base serializers. A controller is operably coupled between the base input demultiplexer and the base data and clock recovery logic to output control signals to the base input demultiplexer in order to change the operating characteristics of the base input demultiplexer, and thus, the size of the data blocks being transmitted. A timer is operably coupled between the plurality of remote deserializers and the second remote output port for determining the skew among the plurality of remote deserializers. The method for minimizing data skew during transmission over a plurality of data lines comprises first simultaneously transmitting a test pattern over the plurality of data lines and receiving the test pattern. Data skew is measured across the plurality of data sets comprising the test pattern, and an inversing data pattern which minimizes the data skew in the data stream is determined. The inversing data pattern for each of the plurality of data sets is communicated to the demultiplexer.

Using multiple high speed serial lines to transmit high data rates while

An improved transceiver that is tightly integrated into an enhanced receiving chip for a computer monitor. The transceiver includes a receiver having a first input port for receiving serialized data, a first output port for transmitting deserialized data to the transceiver, and a second input port adapted for receiving feedback data forwarded from a sensor to an audio and video control unit. The serialized data comprises video, audio and control data. The transceiver further comprises a receiver operably coupled between the first input port and the first output port, as well as a timing generator coupled to recover a clock signal from the serialized data and to synchronize the deserialized data from the recovered clock. The transceiver also includes a transmitter with a third input port for receiving parallel data and a second output port for transmitting a serial data stream. The parallel data are received by the third input port concurrently with the serialized data being received by the first input port. A deserializer is coupled to convert the serialized data into the deserialized data. A serializer is coupled to convert the parallel data into the serial data stream. The transceiver is also part of a communications module, adapted for use in a monitor, also including a timing generator for generating a clock for synchronized timing, control registers for storing native format control data, and a sound generator for producing audio signals which correspond to native format audio data sent to the communications module from a base computer.

Enhanced receiving chip for a computer monitor

An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact. The computer system may include the remote transceiver for transmitting a return serial data stream, a transmitter operably coupled between the feedback input port and the remote serial output port, and a timing generator coupled to recover a clock signal from the serial data stream and to synchronize the deserialized data. The base transceiver may also include a serial input port for receiving the return serial data stream, a receiver operably coupled to the serial input port, and a return high speed serial connection between the remote serial output port and the base serial input port. The return serial data stream is received concurrent with the serial data stream being received.

System for sending data from-and-to a computer monitor using a high

A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Wrap-back test system and method

A character programming method (10) whereby a synchronization character (17) can be determined in a determine encoding scheme operation (12) and a determine synchronization character operation (14). The synchronization character (17) can then be programmed into a synch character logic (26) of an integrated circuit (20) or a core (20) thereof. The synch character logic (26) can be programmed through a plurality of program pins (30) on the periphery of the integrated circuit (20) or by more sophisticated means such as by sending the programming from a sending integrated circuit (40) to a receiving integrated circuit (42) through a communications line (44).

Programmable synchronization character

A test method and means for in integrated circuit (10) having asynchronous communication capabilities including a transmitter (12) and a receiver (14). A pattern generator (24) is provided for generating patterns directly from within the integrated circuit (10). In the best presently known embodiment, a serializer (16) provides a serial output (20) and a deserializer (18) processes a serial input (22) into a parallel signal and provides the parallel signal to a receiver (14). The pattern generator (24) is preprogrammed to provide a parallel data pattern which can optionally and intermittently be provided to the transmitter (12) in a test mode (44). In the test mode (44), signal is routed from the serializer (16) directly to the deserializer (18) via an external loop back path (34) or an internal alternative loop back path (34a). When in the test mode, comparison unit (38) internally generates a pattern identical to that produced by the pattern generator (24) and locks onto signal received from the receiver (14) to perform a functional test (54) and an optional parametric test (58).

Self test of core with unpredictable latency

A loop back test system and method for providing local fault detection within the core or macrocell of an integrated I/O interface device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The loop back of input test data from the transmitters output directly to the receiver's input permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the loop back of serialized, alignment pattern encoded parallel data from the output stage of the I/O transmitter to the receiver's input stage permits identifying faults occurring within the integrated I/O transceiver macrocell. The loop back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Loop-back test system and method

A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

High speed phase locked loop test method and means

Gate level netlists used for timing analysis in integrated circuit design are reduced using a timing shell generator while preserving critical information for timing analysis. After verification of timings, the gate level netlist is convened into a shell containing block boundary information. The function of the shell generator is to delete internal cells meeting a set of criteria. The result is a shell netlist containing a subset of the original netlist. Thus, the design cycle time involved and computing time and resources needed in ASIC development for chips using circuits represented by timing shell netlists are decreased by substituting design verification at the top level of large hierarchical netlists or large flat netlists by bottom up verification procedures using timing shells.

Growing community of inventors

Santa Clara, CA, United States of America

Francois Ducaroir