Texas Instruments Corporation

University of Macau

Marelli Autronica

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

National Semiconductor Corporation

Atmel Corporation

University of Electronic Science and Technology of China

Sgs-thomson Microelectronics Limited

Sgs Microelettronica Spa

Italtel Societa Italiana Telecomunicazione S.p.a.

Italtel Societa Italiana Communicazioni, S.p.a.

Franco Maloberti

Guido Torelli

Rui Paulo Da Silva Martins

Sai-Weng Sin

Martin Kithinji Kinyua

Seng-Pan U

Yan Zhu

Gino Polito

Franco Salerno

U-Fat Chio

Chi-Hang Chan

Siew Kuok Hoon

Jun Chen

Yuanjun Cen

Hua Fan

Hadi Heidari

Jiang Yu

Dagang Li

Daqian Hu

Giuseppe Palmisano

He-Gong Wei

Roberto Rivoir

Edoardo Botti

Ahmad Reza Bahai

James Robert Hochschild

Domenico Rossi

Davide Luigi Brambilla

Gabriele Manganaro

Salvatore Portaluri

Norman L Culp

Feng Ying

Quanyuan Feng

Edoardo Bonizzoni

Masood Yousefi

Huaying Su

Paolo Cacciagrano

Gianmarco Marchesi

Koh Jinseok

Jingxuan Yang

Wem Ming Koe

Jingtao Li

Andrea Oneto

Ermes Viani

Carla Vacchi

Giuseppe Gazzoli

Arunkumar Salimath

Luigi Sforzini

Luciana Coppero

Guido P Torelli

Biao Wang

Li Ding

A converter includes a first switch coupled between a first input terminal and a first terminal of an inductor, and a second switch coupled between a second terminal of the inductor and a second input terminal. A third switch is coupled between the second terminal of the inductor and a first output terminal, and a fourth switch is coupled between the first terminal of the inductor and a second output terminal. A capacitor is coupled between the first and second output terminals. A control circuit monitors a regulated voltage between the first and second output terminals. During a charge phase, the first and second switches are closed to charge the inductor. During a discharge phase, the third and fourth switches are closed to charge the capacitor and increase the regulated voltage.

Electronic converter, related audio system, integrated circuit and method of operating an electronic converter

An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.

Single-loop linear-exponential multi-bit incremental analog-to-digital converter

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C-C; and 4) selecting 64 groups of capacitors from Cto C, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Method for improving spurious free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) of capacitor-resistor combined successive approximation register (SAR) analog-to-digital converter (ADC) by capacitor re-configuration

A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.

Method of arranging capacitor array of successive approximation register analog-to-digital converter

The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.

Analog to digital converter circuit

A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Cascade analog-to-digital converting system

An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Time-interleaved pipelined-SAR analog to digital converter with low power consumption

The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACarray and a sampling capacitor C, an n-type capacitor network including a DACarray and a sampling capacitor C; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.

N-bits successive approximation register analog-to-digital converting circuit

A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator.

Sigma-delta modulator with DAC resolution less than ADC resolution

A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.

DC/DC power converter

Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold signal path for use in a pipelined ADC includes a sample-and-hold circuit configured to operate in two distinct phases. The sample-and-hold circuit includes an input node, an output node, and a power supply node. The power supply node is configured to power down the op amp during one phase and power up the op amp during the other phase. The sample-and-hold stage is configured to provide output during one phase only. Other aspects of the invention include embodiments in which a sample-and-hold stage signal path in a pipelined analog-to-digital converter is configured to accommodate a plurality of parallel outputs.

Methods and circuits for output of sample-and-hold in pipelined ADC

A method for performing parallel digital-to-analog conversion of an n-bit digital input data signal at a frequency of fincluding receiving the n-bit digital input data signal; generating M&#x2212;1 delayed input data signals, M being the number of parallel conversions channels, the M&#x2212;1 delayed input data signals having respective increasing amount of unit delay, the digital input data signal and the M&#x2212;1 delayed input data signals forming M digital signals; holding the M digital signals for a first time period; performing a data transformation of the M digital signals using an M&#xd7;M Hadamard matrix; generating M (n+m)-bit transformed digital data signals; converting each of the M transformed digital data signals to M analog signals; and performing a reverse data transformation of the M analog signals based on the M&#xd7;M Hadamard matrix to generate an output analog signal indicative of the n-bit digital input data signal.

Parallel digital-to-analog-converter

A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.

Driver circuit

Operational amplifier circuits () including error capacitors (C, C) for storing finite gain effect error voltages for correction of output voltages of the circuits (), are disclosed. The circuits () are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter () using the disclosed operational amplifier circuits () is also disclosed.

Switched-capacitor circuits with reduced finite-gain effect

Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Continuous digital background calibration in pipelined ADC architecture

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Torre d'Isola, Italy

Franco Maloberti