Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Franco Lentini

Fabrizio Librizzi

Ignazio Cala'

Giorgio Catanzaro

Pietro Scalia

A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signal is processed and provides the necessary correction to the MOSFET gate signal to equalize the actual anticipation time to the duration of the reference pulse.

Method and relative circuit for generating a control voltage of a synchronous rectifier

A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.

Power supply with magnetic reset of saturable amplifier

Presented is a circuit and method capable to digitally control and, in particular, to control the switching of one or two MOSFETs used as rectifiers in switched mode power supply isolated topologies. Basic circuit implementation of the presented technique is also introduced. A controller has a fixed frequency square wave signal main clock input, generically switching from a low to a high value in two different time intervals. The controller has one or two square wave outputs, swinging from low to high in phase or in opposite with respect to the clock signal. The digital control method is able to generate output signals timed to anticipate output transitions from high to low level with respect to the clock signal transitions. In the control scheme, one or two other secondary inputs set the amount of anticipation time of the respective transitions of the outputs. In isolated SMPS topologies with the PWM controller located on the primary side, the clock signal is derived from the secondary output of the isolation transformer, while the outputs are meant to drive one or two MOSFET gates. The method is able to provide the proper gate drive signals, solving all the known problems in controlling synchronous rectification.

Method and apparatus to digitally control turn-off time of synchronous rectifiers in isolated topologies for switched mode power supplies

A three-state CMOS output buffer circuit includes a final amplifier stage having a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node, and a control circuitry for driving the final amplifier stage including a first logic gate supplied with an input data signal and an enable/disable signal for activating a three-state mode in which the pull-up transistor and the pull-down transistor are both deactivated, the first logic gate driving the pull-up transistor, a second logic gate supplied with said input data signal and enable/disable signal, the second logic gate driving the pull-down transistor. The pull-up transistor has a bulk electrode connected to a switchable bulk line; an auxiliary circuit is provided which as long as a voltage of the output node is not higher than said supply voltage keeps said switchable bulk line connected to the voltage supply. The first logic gate includes circuitry for transferring the voltage of the output node to said switchable bulk line when the voltage of the output node exceeds the supply voltage.

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San Gregorio, Italy

Franco Lentini