Honeywell Information Systems Italia

Bull Hn Information Systems Italia S.p.a.

Franco Ciacci

Giancarlo Tessera

Vincenzo Pizzoferrato

Transparent cache memory for data processing system in which a central processing unit requests the read out of information contained in a working memory at a current address and immediately receives, without waiting, the requested information from the cache memory if the requested information is contained in the cache memory. Meanwhile the cache memory performs the reading and the storing into the cache, of information contained in the working memory at the address next following the current address, so as to advance a possible subsequent request of the central processing unit. If the requested information is not contained in the cache memory, the cache memory performs a double memory read in page mode at the current memory address and at the next following address, thus minimizing the occupation time of the memory. The double reading is performed only for those addresses which allow for page mode operation.

Transparent cache memory

Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time. If I/OP memory access requests are pending, the control unit grants access to the I/OP on a priority basis, activates a memory cycle and monitors in time relation with the memory cycle if other I/OP memory access requests are pending, further granting memory access without delay at the end of the memory cycle. Absent further I/O memory access requests, the control unit resynchronizes its memory access request monitoring with the CPU internal cycles.

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Magenta, Italy

Franco Ciacci