Sgs Microelettronica Spa

Sgsates Componenti Elettronici S.p.a.

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Franco Bertotti

Paolo Ferrari

Mario Foroni

Maria T Gatti

Flavio Francesco Villa

Bruno Murari

Carlo Cini

Giuseppe Ferla

Maurizio Zuffada

Salvatore Rosario Musumeci

Aldo Torazzina

Claudio Contiero

Fabrizio Stefani

Paola Galbiati

Salvatore Raciti

Enrico Novarini

Giuseppe Gavioli

Vincenzo Prestileo

Sergio Garue

Luigi Silvestri

Fausto Catellani

A method of testing a DMOS power transistor that includes arranging a switch between low-voltage circuitry and the gate terminal of the DMOS power transistor, maintaining the switch in an open condition, applying a stress voltage to the gate terminal, testing the functionality of the DMOS power transistor, and, if the test has a positive outcome, short-circuiting the switch through zapping by fusing a normally-open fusible link. An integrated circuit device with DMOS transistor is provided that includes a gate terminal of the DMOS transistor coupled to a control element, a normally-open switch element coupled in series between the gate terminal and the control element and including two metallic regions with an insulating between them connected in parallel with the switch element and in series between the gate terminal and the control element.

Method of testing the gate oxide in integrated DMOS power transistors and integrated device comprising a DMOS power transistor

A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith. In order to prevent latch-ups of the parasite SCR which is formed by the structure of the vertical transistor with insulated collector without limiting the voltage which can be applied between the collector and the emitter thereof to values below the intrinsic breakdown ones, the circuital arrangement comprises an auxiliary PNP transistor the emitter whereof is short-circuited with the emitter of the vertical PNP transistor, the base whereof is connected to the base of the vertical PNP transistor and the collector whereof is connected to the N-type well, and operates as a switch which biases the N-type well at a voltage which is close to the voltage of the emitter of the vertical PNP transistor when the latter is saturated, reverse-biasing the collector/N-well junction, and opens when the vertical PNP transistor is off, limiting the voltage applied to the collector/N-well junction.

Circuital arrangement for preventing latchup in transistors with

The device for shielding the electrons injected towards the substrate by an epitaxial pocket which reaches a negative voltage with respect to said substrate, comprises a debiasing transistor arranged in reverse configuration (with collector and emitter swapped) in the same epitaxial pocket reaching a negative voltage. The transistor is connected with its emitter and its collector between the buried layer of the pocket reaching a negative voltage and the substrate, so as to debias the junction formed by the buried layer and the substrate.

Integrated device for shielding the injection of charges into the

The collector area of a lateral PNP transistor may be incrementally increased during an electic testing step on wafer of an integrated circuit by purposely forming an auxiliary p-type diffused collector region having fractional dimensions near the primary collector region of the transistor and by permanently shorcircuiting the two regions by means of a 'Zener zapping' technique, by forcing a current through the inversely biased base-collector junction utilizing a suitable contact pad connected to the auxiliary collector region to create localized power dissipation conditions sufficient to melt the metal of the respective metal at the adjacent contacts and to form a permanent connection between the two metals. The technique is very useful for adjusting the value of the output current(s) in precision current generating circuits.

Method for incrementally increasing the collector area of a lateral PNP

This integrated device for shielding injected charges in driving circuits for inductive and/or capacitive loads comprises four integrated structures including a first barrier region with high resistivity which surrounds the buried layer of the epitaxial flyback pocket which may be set at a potential lower than ground on the side of the buried layer which faces the driving circuit pocket; a first charge collecting region provided in the epitaxial flyback pocket; a third low-loss diode structure, formed in an epitaxial pocket which is isolated from the flyback pocket and is arranged between the latter and the driving circuit, and connected so as to clamp the voltage between the epitaxial flyback pocket and the substrate to the diode direct conduction voltage; and, finally, a last barrier structure formed by a charge collecting region connected to the supply voltage.

Integrated device for shielding charge injection into the substrate, in

Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.

Monolithically integrated semiconductor device containing bipolar

The structure of a vertical PNP transistor with isolated collector is modified by forming a P-type diffusion outside the perimeter of a sinker collector diffusion to form an auxiliary collector capable of detecting the injection of current toward the substrate when the integrated transistor saturates. The current gathered by said auxiliary collector is used for activating a saturation limiting circuit formed by an NPN transistor which is switched-on when said said current gathered by said auxiliary collector reaches a threshold value and which in turn switches-on a PNP transistor having an emitter and a collector connected respectively to the emitter and to the base of the PNP vertical transistor with isolated collector for reducing the driving base current thereto.

Saturation limiting system for a vertical, isolated collector PNP

This electronic semiconductor device for protecting integrated circuits against electrostatic discharges has a minimal bulk, can withstand high damaging voltages and be produced during the same production phases as the integrated circuit to be protected. The device comprises a pair of diodes connected back to back, arranged between an input of the integrated circuit to be protected and the ground line, with the cathodes connected together and formed by a single semiconductor layer and the anodes formed in a single process phase by employing top-bottom production techniques.

Electronic semiconductor device for protecting integrated circuits

Described is an improved NPN equivalent structure with a breakdown voltage higher than the intrinsic breakdown voltage of the NPN transistor utilizing a complementary PNP transistor and a JFET transistor with the gate connected to ground, the drain connected to the base of the PNP and the source connected to the collectors of the complementary pair. An integrated form of the structure is particularly advantageous and the equivalent NPN transistor is substantially exempt from Early effect and has improved output current capacity.

NPN equivalent structure with breakdown voltage greater than the

Described is an integrated semiconductor structure for the protection from electrical discharges of electrostatic origin of particularly sensitive components of an integrated circuit. The structure is almost entirely formed directly underneath a particular input pad thus requiring a minimum useful area and is characterized by very high damaging voltage and speed of intervention because of the extremely low series resistance of the two zener junctions constituting the structure.

Protection of integrated circuits from electric discharge

This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set thickness and fully covering the resistor. Thus, the resulting resistor is unaffected by any subsequent thermal treatments and its value remains constant irrespective of any high potential metal layers or connections crossing it. The method affords in particular resistive values of the order of 1 kOhms/square.

Method of making an implanted resistor, and resistor obtained thereby

This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.

Power transistor with spaced subtransistors having individual collectors

A power transistor comprising a plurality of elementary transistors coupled in parallel and an identical number of current generators, each of which has a terminal coupled individually to the base of an elementary transistor is described. High power levels may be achieved with a transistor of this type without forward secondary breakdown taking place.

Bipolar power transistor

A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.

Buried-resistance semiconductor device and fabrication process

A monolithic semiconductor device including an integrated control circuit and a pair of power transistors in a Darlington configuration integrated in the same chip solves the problem of ON-OFF switching which is prevented by the presence of parasitic transistors within the structure, these transistors preventing the correct operation of the device at saturation. The solution involves a suitable arrangement of the components in the chip, with the output transistor of the Darlington pair disposed in an intermediate position between the drive transistor of the pair and the integrated control circuit. The addition of semiconductor shields, disposed between the output transistor of the Darlington pair and the integrated control circuit further reduces the damaging effects of the parasitic transistors.

Growing community of inventors

Milan, Italy

Franco Bertotti