Imec Vzw

Imec

Interuniversitair Microelektronica Centrum (imec)

Katholieke Universiteit Leuven

Katholieke Universiteit Leuven, Ku Leuven R&d

Stichting Imec Nederland

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Samsung Electronics Co., Ltd.

Other

Siemens Aktiengesellschaft

Texas Instruments Corporation

Shanghaitech University

Universidad Complutense De Madrid

Vib Vzw

Universiteit Hasselt

Francky Catthoor

Praveen Raghavan

Hugo De Man

Miguel Miranda

Antonis Papanikolaou

Stefan Cosemans

Hua Wang

Paul Marchal

Dimitrios Rodopoulos

Erik Brockmeyer

Maria-Iro Baka

Komalan Manu Perumkunnil

Sven Wuytack

Jose Ignacio Gomez

Jos Huisken

Julien Ryckaert

Juergen Boemmels

Wim Dehaene

Vibhu Sharma

Bert Gyselinckx

Pieter Weckx

Marc Engels

Bruno Bougard

Odysseas Zografos

Liesbet Van Der Perre

Sofie Pollin

Curt Schurgers

Jochen Uwe Giese

Maryam Ashouei

Gregory Lenoir

Nathalie Cossement

Patrizio Manganiello

Peng Yang

Chun Wong

Aggeliki Prayati

Rudy Lauwereins

Johannes Goverde

Koen Danckaert

Robert Fasthuber

Edouard Giacomin

Matthias Hartmann

Stefan Janssens

Christian Tenllado

Xavier Rottenberg

Karen Irma Maex

Andy Lambrechts

Davide Bruni

Yajun Ha

Alessio Spessot

Jef Poortmans

Jan Genoe

Murali Jayapala

Allert Van Zelst

Azad Naeemi

Peter Schelkens

Diederik Verkest

Vikas Dubey

Benjamin Kaczer

Xinzhe Liu

Sourav Dutta

Daniele Garbin

David Blinder

Wim Van Thillo

Fupeng Chen

Frederik Naessens

Bhanu Kapoor

Eddy De Greef

Christos Baloukas

Anup Kumar Das

Dimitrios Soudris

Absar Javed

Martin Janssen

Dimitrios Anagnostos

Hans Goverde

Christiaan Baert

Jin Guo

Arnout Vandecappelle

Tycho Van Meeuwen

Mohit Dandekar

Ittetsu Taniguchi

Daichi Watari

Jean-Philippe Diguet

Johan D'Eer

Cedric Ghez

Satyakiran N Munaga

Julio L Da Silva Junior

Evangelos Bempelis

Chidamber Kulkarni

Elena Hammari

Per Gunnar Kjeldsberg

Michael Van Swaaij

Hans Samsom

Satya Munaga

Frank Franssen

Mohamed Sabry

Zhe Ma

Sotiris Xydis

David Atienza Alonso

David Novo Bruna

Javier Setoain Rodrigo

Example embodiments relate to methods for disseminating scaling information and applications thereof in very large scale integration (VLSI) implementations of fixed-point fast Fourier transforms (FFTs). One embodiment includes a method for disseminating scaling information in a system. The system includes a linear decomposable transformation process and an inverse process of the linear decomposable transformation process. The inverse process of the linear decomposable transformation process is defined, in time or space, as an inverse linear decomposable transformation process. The linear decomposable transformation process is separated from the inverse linear decomposable transformation process. The linear decomposable transformation process or the inverse linear decomposable transformation process is able to be performed first and is defined as a linear decomposable transformation I. The other remaining process is performed subsequently and is defined as a linear decomposable transformation II. The method for disseminating scaling information is used for a bit width-optimized and energy-saving hardware implementation.

Method for disseminating scaling information and application thereof in VLSI implementation of fixed-point FFT

The disclosed 3D IC includes a plurality of vertically stacked device tiers, each device tier comprising an SRAM circuit, each SRAM circuit comprising an SRAM bit cell, wherein the bit cells are stacked on top of each other to define a stack of bit cells and wherein and each bit cell comprises first and second pass transistors, first pull-up and pull-down transistors, and second pull-up and pull-down transistors. The SRAM circuits have an identical layout and each SRAM circuit comprises: a single active layer forming an active semiconductor pattern of the transistors of the bit cell, and a single routing layer of horizontally routed conductive lines comprising a complementary pair of first and second bit lines connected to the bit cell of the SRAM circuit, gate lines defining gates of the transistors of the bit cell of the SRAM circuit, and wiring lines forming interconnections of the bit cell of the SRAM circuit.

3D integrated circuit

A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

System and method of simulating aging in device circuits

A system and for distributing data for 3D light field projection and a method thereof. The system comprises input terminals and output terminals that are connectable to pixel elements of a display. Data paths are established between input terminals and output terminals, and are controlled by data switches. The system also comprises a control plane adapted for applying control variables to the data switches. Control switches of the control plane select the control variables which are applied to the data switches. Sequences of control variables and enable variables propagate along at least one first delay line and along at least one second delay line, respectively. Delay units of the at least one first delay line and of the at least one second delay line have a synchronous relationship. During system run-time patterns contained in the stream of input data are detected for determining the sequences of control variables.

Data distribution for holographic projection

A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

Complexity-reduced simulation of circuit reliability

According to an aspect of the present inventive concept there is provided 3D IC, comprising:

3D integrated count

A localized smart energy management system comprises a plurality of controllable loads, at least one intermittent energy source, a selectively connectable dispatchable energy source, and optionally an energy storage system. A method for balancing power production and power consumption of such localized smart energy management systems in real time comprises performing a coarse-grained optimization in a first layer of a hierarchical optimization structure to generate a predicted schedule, based on long-term load demand profiles and long-term power generation profiles. A second layer iteratively refines the predicted schedule upon receiving a new forecast of a short-term power generation profile for the at least one intermittent energy source.

Multi-scale optimization framework for smart energy systems

A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.

Convolution engine for neural networks

A method for generating/updating a database of current-voltage characteristic curves is disclosed. This method includes simulating for at least one combination of a topology of a photovoltaic cell group, an internal cell temperature(s) and a cell irradiation(s), a model of the photovoltaic cell group to provide a representative current-voltage characteristic curve, and clustering the current-voltage characteristic curves to identify at least one plurality of similar current-voltage characteristic curves. The method also includes generating a many-to-one mapping in the database to map query requests corresponding to each of the at least one plurality of similar current-voltage characteristic curves onto a single representative current-voltage characteristic curve for that plurality, each query request identifying a topology of a photovoltaic cell group, at least one internal temperature for the photovoltaic cells in the photovoltaic cell group and at least one cell irradiation for the photovoltaic cells in the photovoltaic cell group.

Simulation of photovoltaic systems

A computer-implemented method and related device are disclosed for determining a plurality of operating scenarios of an energy system. The method comprises obtaining a plurality of performance measures of the energy system as a function of time corresponding to a plurality of sets of values of input variables. The method comprises clustering the plurality of sets of values of the input variables and the performance measures associated therewith into groups and defining a descriptor for each of the groups. The method also comprises outputting the descriptors of the groups for use in an online prediction or offline estimation of the energy system.

Method and device for determining energy system operating scenario

A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

Control plane organization for flexible digital data plane

A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over &#x3c0; with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

Plasmonic devices and circuits

The present disclosure relates to reconfigurable voltaic modules. One example embodiment includes a photovoltaic module. The photovoltaic module includes a plurality of photovoltaic cells arranged in a grid having logical rows and columns. The photovoltaic module also includes a plurality of non-reconfigurable interconnects electrically interconnecting subsets of the plurality of photovoltaic cells to form a plurality of cell strings. In addition, the photovoltaic module includes a plurality of reconfigurable interconnects. Each cell string includes at least four photovoltaic cells connected in an electrical series from a first cell to a last cell, the first cell and the last cell being located on a same edge of the grid.

Reconfigurable photovoltaic module

The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Memory structure comprising scratchpad memory

Growing community of inventors

Temse, Belgium

Francky Catthoor