Stmicroelectronics S.a.

Franck Roche

Dragos Davidescu

Ludovic Ruat

Sandrine Lendre

Olivier Plourde

Philippe Basset

Pascal Narche

Didier Cavalli

André Colomb

Pierre Tarayre

Gosagan Padmanabhan

Thierry Bouquier

The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Synchronous data transmission method

The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Method for managing a microprocessor stack for saving contextual data

A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

Microprocessor having an extended addressable space

A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

Harvard architecture microprocessor having a linear addressable space

A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one instruction for exchanging the contents of both memory locations. The microprocessor includes an additional internal register connected to an output of the arithmetic and logic unit, and transfers the contents of a first one of the memory locations to be exchanged into the additional register when executing the instruction set. The microprocessor further transfers the contents of a second one of the memory locations to be exchanged into the first memory location, and transfers the contents of the additional register into the second memory location.

Microprocessor having instructions for exchanging values between two registers or two memory locations

A microprocessor is provided with protection circuits to secure access to its registers. The microprocessor includes a plurality of protection circuits, each associated with a register of the microprocessor. The protection circuits automatically block selection of the registers after each resetting of the microprocessor. The releasing of a protection circuit associated with a register is done by the successive sending, on the data bus, of N passwords proper to the register during N first operations for the selection of the register with N&#x2267;1. The selection of the register is effective only for the subsequent operations for selection of the register up to the next resetting of the microprocessor.

Microprocessor with protection circuits to secure the access to its registers

A microprocessor includes a counter having a counting input and a reset input. The counting input is coupled to a first terminal of the microprocessor for the selection of an operating mode thereof by application of a predetermined number of pulses to the first terminal. The reset input of the counter is driven by a control signal present on a second terminal of the microprocessor. The control signal is maintained by default at a first logic value ensuring the maintaining at zero of the counter during the initialization period by a circuit internal or external the microprocessor. Immunity against electromagnetic perturbations causing the microprocessor to enter into the test mode is provided.

Method and apparatus for preventing a microprocessor from erroneously entering into a test mode during initialization

The present invention relates to an integrated circuit comprising a first clock circuit delivering a first clock signal, a second clock circuit delivering a second clock signal, a first counting circuit for delivering a time base signal using a clock signal and a counting value, and means for applying the first clock signal and a first counting value to the first counting circuit, so as to produce a first time base signal. According to the present invention, the integrated circuit comprises means for producing a second time base signal using the second clock signal and a second counting value, and means for calibrating the second counting value such that it is equal or proportional to the number of periods of the second clock signal occurring during a determined time interval equal to a period or to a whole number of periods of the first time base signal. Application particularly to the management of a timer in a microprocessor.

Microprocessor comprising a self-calibrated time base circuit

A microprocessor may be switchable between a normal mode and a test mode for performing a test program and may include a central processing unit (CPU) for saving contextual data in a stack of the microprocessor at the time of switching to the test mode. The CPU may deliver, at the beginning of the test program and on an input/output port, contextual data present in the stack beginning with the top of the stack. The CPU may also decrement a stack pointer by a value corresponding to a number of contextual data delivered.

Microprocessor for saving contextual data when switching to a test program

A method and device reduces consumption of a microcontroller, allowing the microcontroller to enter into an &ldquo;active halt&rdquo; mode in which the central processing unit, the internal peripheral circuits, and a clock tree are deactivated. The main oscillator is operative and delivers an oscillating signal. An internal interruption returns the microcontroller back into the run mode and is generated after a time delay obtained by an internal circuit activated by the oscillating signal.

Method and device for reducing current consumption of a microcontroller

A method for managing interrupts in a microprocessor includes interrupts having a two-fold order of priority, i.e., a software priority and a hardware priority, wherein the microprocessor operates in two modes. During a first mode, the execution of an interrupt routine cannot be interrupted by the arrival of a new interrupt, even if it is a priority interrupt, unless this new interrupt is non-maskable. During a second mode, the execution of an interrupt routine is interrupted by the arrival of a priority interrupt. At the time of the execution of an interrupt, its software priority level is loaded into the state register of the microprocessor.

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Trets, France

Franck Roche