Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Franck Bassani

Jean-Michel Hartmann

Thierry Baron

Etienne Eustache

Bassem Salem

Mohamed-Aymen Mahjoub

A method for the nanoscale etching of a layer of GeSnon a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of GeSnusing a mixture comprising dichlorine (Cl) and dinitrogen (N) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of GeSnon the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of GeSnaccording to the etching method. A conduction channel made of GeSnfor a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of GeSn.

Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor

A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miof width L, of height hwith a distance S between masking patterns; growth of patterns Miof III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height h, the growth step comprising: determining growth rates vand vat right angles to the face of the III-V material, defining ratio R=v/v; determining the angle of dislocations &#x3b8; of the III-V material relative to the plane of the substrate; determining the critical minimum height hby the equation: with R being determined to be greater than tan(&#x3b8;).

Optimized method for fabricating patterns of III-V semiconductor material on a semiconductor substrate

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Echirolles, France

Franck Bassani