Nxp B.v.

U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Nxp USA, Inc.

Koninklijke Phillips Electronics N.v.

Franciscus Petrus Widdershoven

Michiel Slotboom

Jan Haisma

Erwin Rinaldo Meinders

Robertus Adrianus Maria Wolters

Martijn Henri Richard Lankhorst

Viet Nguyen

Gerjan F Van De Walle

Evelyne Gridelet

David Van Steenwinckel

Jurriaan Schmitz

Sebastian Egner

Anne Johan Annema

Thomas Merelle

Nicole Anne Helena Freddy Wils

Jan Leo Dominique Fransaer

Mark Thomas Johnson

Roel Daamen

Paul Kimelman

Adrianus Sempel

Radu Surdeanu

Antonius Hendrikus Jozef Kamphuis

Roger Cuppens

Wibo Daniel Van Noort

Brian Christopher Kahne

Viet Thanh Dinh

Aart A Van Gorkum

Marnix G Collet

Andreas Bernardus Maria Jansman

Romano Hoofman

Dimitri Soccol

Wilhelmus Sebastianus Marcus Maria Ketelaars

Michiel Jos Van Duuren

Rameswor Shrestha

Adam Fuks

Anthonie Meindert Herman Ditewig

Robertus A M Wolters

Gerjan Franciscus Arthur Van De Walle

Pablo Garcia Tello

Peter Van De Haar

Martijn H R Lankhorst

Xiaomin Lu

Marcellinus J M Pelgrom

Magali Lambert

Dimitri Soccoi

Gerard Reuvers

Maurits M N Storms

Marcus Henricus Van Kleef

Arie J De Kock

Wibo D Van Noort

Wilhelmus S M M Ketelaars

A scalable neural network accelerator may include a first circuit for selecting a sub array of an array of registers, wherein the sub array comprises LH rows of registers and LW columns of registers, and wherein LH and RH are integers. The accelerator may also include a register for storing a value that determines LH. In addition, the accelerator may include a first load circuit for loading data received from the memory bus into registers of the sub array.

Scalable neural network accelerator architecture

Embodiments are provided for a packaged semiconductor device including: a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; and a top cover including a soft-magnetic material positioned on the back side of the semiconductor die, wherein the top cover includes a recess formed in a first major surface of the top cover, the first major surface faces the back side of the semiconductor die, and the recess is positioned over the MRAM cell array.

Magnetic shielding structure for MRAM array

In an embodiment, a method for analyzing signals from a pixelated capacitive sensor is disclosed. The method involves classifying capacitance signals from sensor cells of a pixelated capacitive sensor into at least one class based on capacitance values for sensor cells indicated by corresponding capacitance signals and assigning an attribute to sensor cells based on the classification of the corresponding capacitance signals.

Method and system for analysis of pixelated capacitive sensor signals

Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.

Device and method for detecting semiconductor substrate thickness

A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+T. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time T, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

Sensor circuit and method

A secure electronic apparatus and a method for determining that a secure electronic apparatus has been tampered with. The apparatus includes a memory and a plurality of sensors which each to receive an input signal and output a digital signal determined by the input signal and by a physical quantity sensed by the sensor (e.g. capacitance). A measurement routine includes applying a plurality of input signal values to the sensors and, for each input signal value, using the digital output signals of each sensor to determine a combined output result. The combined output results of the measurement routine are compared with a set of combined output results stored in the memory. A detected a difference between the combined output results of the measurement routine and the set of combined output results stored in the memory can be used to determine that the secure electronic apparatus has been tampered with.

Secure electronic apparatus and method

A lateral test flow arrangement for a test molecule is disclosed, comprising: a test strip for transporting an analyte away from a sampling region and towards an absorbing region, the test strip having therein and remote from the sampling region, a test region for functionalization with a molecule which binds to the test molecule or to a conjugate of the test molecule; a sensing test capacitor having electrodes extending across the test strip at least partially aligned with the test region and being physically isolated therefrom; a reference test capacitor having electrodes extending across the test strip and being physically isolated therefrom; and an electronic circuit configured to measure a time-dependant capacitance difference between the sensing test capacitor and the reference test capacitor. A method for carrying out that lateral flow tests is also disclosed, as are test systems and in particular pregnancy test systems.

Electronic lateral flow test arrangement and method

A sensor device has an arrangement of plural sensors for sensing an analyte which is in at least one of liquid phase or a suspension or a gel. Each sensor includes a nano-electrode and is configured to sense the presence of a particle localized to or bound to the nano-electrode. The sensor is configured to discriminate in real-time the binding of particles to respective nano-electrodes.

Sensor, a sensor array, and a method of operating a sensor

'Click-assembly' methods of assembling a sensor for sensing biologically-active molecules by measuring impedance changes, are disclosed, comprising supporting a bio-sensor on a carrier, the bio-sensor comprising an electronic component having at least one micro-electrode and at least one electrical contact, functionalizing the bio-sensor by physically or chemically coupling a bio-receptor molecule to each of the at least one micro-electrode, and subsequently assembling the bio-sensor with a micro-fluidic unit by means of a clamp which clamps the bio-sensor with the micro-fluidic unit, such that in use a fluid introduced into the micro-fluidic unit is able to contact the bio-receptor and is isolated from the electrical contact. The clamp may be a spring, and the method may avoid a requirement for sealing by chemical or thermal means and thereby avoid damaging the bio-receptor. Sensors which can be assembled according to such methods are also disclosed.

Sensor and a method of assembling a sensor

A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au&#x2014;Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au&#x2014;Cu alloy electrodes is also disclosed.

Semiconductor device having Au&#x2014;Cu electrodes, and method of manufacturing semiconductor device

A sensor chip () for detecting particles, the sensor chip () comprising a substrate (), an electric connection structure () arranged in a surface portion of the substrate () and adapted for an electric connection to an electric connection element (), a sensor active region () arranged in another surface portion of the substrate () and being sensitive to the presence of the particles to be detected, and a continuous dielectric layer () covering the substrate () including covering the electric connection structure () and the sensor active region ().

Sensor chip and method of manufacturing the same

Semiconductor device having Au-Cu electrodes, and method of manufacturing semiconductor device

A module comprises a bus invert encoder () for determining whether a set of data bits should be inverted prior to transmission over a communication bus. The bus invert encoder () produces a bus invert signal BI which controls a selective inversion means (), for example a multiplexer. A partial fault detection encoder () determines one or more temporary check bits from the set of data bits, substantially in parallel with the bus invert encoder (). Thus, the one or more temporary check bits are determined based on the assumption that the set of data bits are to be transmitted without inversion from the selective inversion means (). A logic unit () is provided for correcting the one or more temporary check bits, if necessary, based on the bus invert signal produced by the bus invert encoder (). The module has the e advantage of enabling the temporary check bits to be determined in parallel with the bus invert encoding, thereby reducing latency, with the logic unit being used to correct the check bits, if necessary, prior to transmission over the communication bus.

Integrated circuit with memory cells comprising a programmable resistor and method for addressing memory cells comprising a programmable resistor

An RFID tag (') comprises at least one antenna (&#x2032;) and electronic tag components () cooperating with the antenna, wherein the antenna (&#x2032;) and the electronic tag components () are positioned on a common substrate (), wherein portions () of the substrate encircled by the antenna (&#x2032;) and not occupied by the electronic tag components () have been removed.

RFID tag and method of fabricating an RFID tag

The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.

Electric device comprising phase change material

Growing community of inventors

Eindhoven, Netherlands

Franciscus Petrus Widdershoven